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1. 发明授权

US09454366B2 Copying character data having a termination character from one memory location to another 有权
标题翻译：将具有终止字符的字符数据从一个存储器位置复制到另一个存储器位置
公开(公告)号：US09454366B2
公开(公告)日：2016-09-27
申请号：US13421498
申请日：2012-03-15
申请人： Jonathan D. Bradbury , Michael K. Gschwind , Timothy J. Slegel
发明人： Jonathan D. Bradbury , Michael K. Gschwind , Timothy J. Slegel
IPC分类号： G06F12/00 , G06F9/30
CPC分类号： G06F9/30018 , G06F9/30021 , G06F9/30036 , G06F9/30043
摘要： Copying characters of a set of terminated character data from one memory location to another memory location using parallel processing and without causing unwarranted exceptions. The character data to be copied is loaded within one or more vector registers. In particular, in one embodiment, an instruction (e.g., a Vector Load to block Boundary instruction) is used that loads data in parallel in a vector register to a specified boundary, and provides a way to determine the number of characters loaded. To determine the number of characters loaded (a count), another instruction (e.g., a Load Count to Block Boundary instruction) is used. Further, an instruction (e.g., a Vector Find Element Not Equal instruction) is used to find the index of the first delimiter character, i.e., the first termination character, such as a zero or null character within the character data. This instruction checks a plurality of bytes of data in parallel.
摘要翻译：使用并行处理将一组终止的字符数据的字符从一个存储器位置复制到另一个存储器位置，并且不引起无理的异常。要复制的字符数据被加载到一个或多个向量寄存器中。特别地，在一个实施例中，使用将矢量寄存器中并行的数据加载到指定边界的指令（例如，向量块向量边界指令），并且提供了确定加载的字符数的方法。为了确定加载的字符数（计数），使用另一条指令（例如，向块边界指令的加载计数）。此外，使用指令（例如，矢量查找元素不等于指令）来找到第一分隔符字符的索引，即第一终止字符，例如字符数据内的零或空字符。该指令并行地检查多个字节的数据。

2. 发明授权

US09405541B2 Run-time instrumentation indirect sampling by address 有权
标题翻译：运行时间仪器间接采样地址
公开(公告)号：US09405541B2
公开(公告)日：2016-08-02
申请号：US13422550
申请日：2012-03-16
申请人： Jonathan D. Bradbury , Charles W. Gainey, Jr. , Michael K. Gschwind
发明人： Jonathan D. Bradbury , Charles W. Gainey, Jr. , Michael K. Gschwind
IPC分类号： G06F11/34 , G06F11/36 , G06F9/30
CPC分类号： G06F11/3644 , G06F9/3005 , G06F9/30058 , G06F9/30076 , G06F9/30145 , G06F9/45533 , G06F11/3466 , G06F11/348 , G06F11/3612 , G06F11/362 , G06F11/3636 , G06F11/3648 , G06F11/3664 , G06F2201/86 , G06F2201/87
摘要： The invention relates to implementing run-time instrumentation indirect sampling by address. An aspect of the invention includes a method for implementing run-time instrumentation indirect sampling by address. The method includes reading sample-point addresses from a sample-point address array, and comparing, by a processor, the sample-point addresses to an address associated with an instruction from an instruction stream executing on the processor. The method further includes recognizing a sample point upon execution of the instruction associated with the address matching one of the sample-point addresses. Run-time instrumentation information is obtained from the sample point. The method also includes storing the run-time instrumentation information in a run-time instrumentation program buffer as a reporting group.
摘要翻译：本发明涉及通过地址实现运行时仪表间接采样。本发明的一个方面包括一种通过地址实现运行时间仪表间接采样的方法。该方法包括从采样点地址阵列中读取采样点地址，以及将处理器将采样点地址与来自在处理器上执行的指令流的指令相关联的地址进行比较。该方法还包括在执行与匹配其中一个采样点地址的地址相关联的指令时识别采样点。从采样点获取运行时仪表信息。该方法还包括将运行时仪器信息存储在作为报告组的运行时仪表程序缓冲器中。

3. 发明授权

US09367316B2 Run-time instrumentation indirect sampling by instruction operation code 有权
标题翻译：运行时间仪表通过指令操作代码进行间接采样
公开(公告)号：US09367316B2
公开(公告)日：2016-06-14
申请号：US13422563
申请日：2012-03-16
申请人： Jonathan D. Bradbury , Charles W. Gainey, Jr. , Michael K. Gschwind , Eric M. Schwarz
发明人： Jonathan D. Bradbury , Charles W. Gainey, Jr. , Michael K. Gschwind , Eric M. Schwarz
IPC分类号： G06F9/44 , G06F9/30 , G06F11/36 , G06F11/34
CPC分类号： G06F9/30145 , G06F9/3005 , G06F9/30058 , G06F11/3466 , G06F11/348 , G06F11/3644 , G06F2201/86 , G06F2201/88
摘要： Embodiments of the invention relate to implementing run-time instrumentation indirect sampling by instruction operation code. An aspect of the invention includes reading sample-point instruction operation codes from a sample-point instruction array, and comparing, by a processor, the sample-point instruction operation codes to an operation code of an instruction from an instruction stream executing on the processor. A sample point is recognized upon execution of the instruction with the operation code matching one of the sample-point instruction operation codes. The run-time instrumentation information is obtained from the sample point. The run-time instrumentation information is stored in a run-time instrumentation program buffer as a reporting group.
摘要翻译：本发明的实施例涉及通过指令操作代码实现运行时间仪表间接采样。本发明的一个方面包括从采样点指令阵列读取采样点指令操作码，并将处理器将采样点指令操作码与来自在处理器上执行的指令流的指令的操作码进行比较。在执行指令时，识别采样点，其中操作码与采样点指令操作码之一匹配。从采样点获取运行时仪表信息。运行时仪表信息作为报告组存储在运行时仪表程序缓冲区中。

4. 发明授权

US09354888B2 Performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching 有权
标题翻译：结合预解码时间优化指令序列缓存执行预解码时间优化指令
公开(公告)号：US09354888B2
公开(公告)日：2016-05-31
申请号：US13432357
申请日：2012-03-28
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/382 , G06F9/3017 , G06F9/3808 , G06F9/384
摘要： A method for performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching. The method includes receiving a first instruction of an instruction sequence and a second instruction of the instruction sequence and determining if the first instruction and the second instruction can be optimized. In response to the determining that the first instruction and second instruction can be optimized, the method includes, preforming a pre-decode optimization on the instruction sequence and generating a new second instruction, wherein the new second instruction is not dependent on a target operand of the first instruction and storing a pre-decoded first instruction and a pre-decoded new second instruction in an instruction cache. In response to determining that the first instruction and second instruction can not be optimized, the method includes, storing the pre-decoded first instruction and a pre-decoded second instruction in the instruction cache.
摘要翻译：一种执行预解码时间优化指令并结合预解码时间优化指令序列缓存的方法。该方法包括接收指令序列的第一指令和指令序列的第二指令，并且确定是否可以优化第一指令和第二指令。响应于确定可以优化第一指令和第二指令，该方法包括：对指令序列执行预解码优化并产生新的第二指令，其中新的第二指令不依赖于目标操作数所述第一指令并将预解码的第一指令和预解码的新的第二指令存储在指令高速缓存中。响应于确定第一指令和第二指令不能被优化，该方法包括：将预解码的第一指令和预解码的第二指令存储在指令高速缓存中。

5. 发明授权

US09323529B2 Reducing register read ports for register pairs 有权
标题翻译：减少寄存器对的寄存器读端口
公开(公告)号：US09323529B2
公开(公告)日：2016-04-26
申请号：US13552099
申请日：2012-07-18
申请人： Jonathan D. Bradbury , Michael K. Gschwind
发明人： Jonathan D. Bradbury , Michael K. Gschwind
IPC分类号： G06F9/30 , G06F15/76
CPC分类号： G06F9/30141 , G06F9/30 , G06F9/30014 , G06F9/3005 , G06F9/30098 , G06F9/30185
摘要： Embodiments relate to reducing a number of read ports for register pairs. An aspect includes executing an instruction. The instruction identifies a pair of registers as containing a wide operand which spans the pair of registers. It is determined if a pairing indicator associated with the pair of registers has a first value or a second value. The first value indicates that the wide operand is stored in a wide register, and the second value indicates that the wide operand is not stored in the wide register. Based on the pairing indicator having the first value, the wide operand is read from the wide register. Based on the pairing indicator having the second value, the wide operand is read from the pair of registers. An operation is performed using the wide operand.
摘要翻译：实施例涉及减少用于寄存器对的多个读端口。一方面包括执行指令。该指令将一对寄存器标识为包含跨越寄存器对的宽操作数。确定与该对寄存器相关联的配对指示符是否具有第一值或第二值。第一个值表示宽操作数存储在宽寄存器中，第二个值表示宽操作数不存储在宽寄存器中。基于具有第一值的配对指示符，从宽寄存器读取宽操作数。基于具有第二值的配对指示符，从该对寄存器读取宽操作数。使用宽操作数执行操作。

6. 发明授权

US09286072B2 Using register last use infomation to perform decode-time computer instruction optimization 有权
标题翻译：使用寄存器最后使用信息执行解码时间计算机指令优化
公开(公告)号：US09286072B2
公开(公告)日：2016-03-15
申请号：US13251486
申请日：2011-10-03
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30181 , G06F9/30167 , G06F9/3017 , G06F9/3832 , G06F9/384 , G06F9/3851
摘要： Two computer machine instructions are fetched for execution, but replaced by a single optimized instruction to be executed, wherein a temporary register used by the two instructions is identified as a last-use register, where a last-use register has a value that is not to be accessed by later instructions, whereby the two computer machine instructions are replaced by a single optimized internal instruction for execution, the single optimized instruction not including the last-use register.
摘要翻译：两台计算机机器指令被取出执行，而被一个要执行的优化指令所代替，其中由两个指令使用的临时寄存器被识别为最后使用寄存器，其中最后使用寄存器的值不是由后来的指令访问，由此两个计算机机器指令被用于执行的单个优化的内部指令代替，单个优化的指令不包括最后使用的寄存器。

7. 发明授权

US09280348B2 Decode time instruction optimization for load reserve and store conditional sequences 有权
公开(公告)号：US09280348B2
公开(公告)日：2016-03-08
申请号：US13432404
申请日：2012-03-28
申请人： Michael K. Gschwind
发明人： Michael K. Gschwind
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30196 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/30145 , G06F9/3017 , G06F9/3844
摘要： A technique is provided for replacing an atomic sequence. A processing circuit receives the atomic sequence. The processing circuit detects the atomic sequence. The processing circuit generates an internal atomic operation to replace the atomic sequence.

8. 发明授权

US08615746B2 Compiling code for an enhanced application binary interface (ABI) with decode time instruction optimization 失效
标题翻译：使用解码时间指令优化编译用于增强应用二进制接口（ABI）的代码
公开(公告)号：US08615746B2
公开(公告)日：2013-12-24
申请号：US13459594
申请日：2012-04-30
申请人： Robert J. Blainey , Michael K. Gschwind , James L. McInnes , Steven J. Munroe
发明人： Robert J. Blainey , Michael K. Gschwind , James L. McInnes , Steven J. Munroe
IPC分类号： G06F9/45
CPC分类号： G06F8/41 , G06F8/443 , G06F8/54
摘要： Compiling code for an enhanced application binary interface (ABI) including identifying, by a computer, a code sequence configured to perform a variable address reference table function including an access to a variable at an offset outside of a location in a variable address reference table. The code sequence includes an internal representation (IR) of a first instruction and an IR of a second instruction. The second instruction is dependent on the first instruction. A scheduler cost function associated with at least one of the IR of the first instruction and the IR of the second instruction is modified. The modifying includes generating a modified scheduler cost function that is configured to place the first instruction next to the second instruction. An object file is generated responsive to the modified scheduler cost function. The object file includes the first instruction placed next to the second instruction. The object file is emitted.
摘要翻译：编译用于增强型应用二进制接口（ABI）的代码，包括由计算机识别被配置为执行可变地址参考表函数的代码序列，所述变量地址参考表函数包括对可变地址参考表中位置之外的偏移量的变量的访问。代码序列包括第一指令的内部表示（IR）和第二指令的IR。第二条指令取决于第一条指令。与第一指令的IR和第二指令的IR中的至少一个相关联的调度器成本函数被修改。修改包括生成被配置为将第一指令放置在第二指令旁边的修改的调度器成本函数。响应于修改的调度器成本函数生成对象文件。目标文件包括放置在第二条指令旁边的第一条指令。目标文件被发出。

9. 发明申请

US20130339652A1 Radix Table Translation of Memory 有权
标题翻译：记忆基数表翻译
公开(公告)号：US20130339652A1
公开(公告)日：2013-12-19
申请号：US13517758
申请日：2012-06-14
申请人： Anthony J. Bybell , Michael K. Gschwind
发明人： Anthony J. Bybell , Michael K. Gschwind
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/1018 , G06F12/1027 , G06F12/1036
摘要： Embodiments relate to managing memory page tables in a processing system. A request to access a desired block of memory is received. The request includes an effective address that includes an effective segment identifier (ESID) and a linear address, the linear address including a most significant portion and a byte index. An entry in a buffer that includes the ESID of the effective address is located. Based on the entry including a radix page table pointer (RPTP), performing: using the RPTP to locate a translation table of a hierarchy of translation tables, using the located translation table to translate the most significant portion of the linear address to obtain an address of a block of memory, and based on the obtained address, performing the requested access to the desired block of memory.
摘要翻译：实施例涉及在处理系统中管理存储器页表。接收访问所需存储块的请求。该请求包括有效地址，其包括有效段标识符（ESID）和线性地址，线性地址包括最高有效部分和字节索引。位于包含有效地址的ESID的缓冲区中的条目。基于包括基数表指针（RPTP）的条目，执行：使用RPTP来定位转换表的层次结构的转换表，使用定位的转换表来翻译线性地址的最高有效部分以获得地址的存储器块，并且基于获得的地址，执行对期望的存储器块的所请求的访问。

10. 发明申请

US20130339651A1 MANAGING PAGE TABLE ENTRIES 有权
标题翻译：管理页表
公开(公告)号：US20130339651A1
公开(公告)日：2013-12-19
申请号：US13517738
申请日：2012-06-14
申请人： Anthony J. Bybell , Michael K. Gschwind
发明人： Anthony J. Bybell , Michael K. Gschwind
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/1027 , G06F2212/652 , G06F2212/683
摘要： Embodiments relate to managing page table entries in a processing system. A first page table entry (PTE) of a page table for translating virtual addresses to main storage addresses is identified. The page table includes a second page table entry contiguous with the second page table entry. It is determined whether the first PTE may be joined with the second PTE, based on the respective pages of main storage being contiguous. A marker is set in the page table for indicating that the main storage pages identified by the first PTE and second PTEs are contiguous.
摘要翻译：实施例涉及在处理系统中管理页表条目。识别用于将虚拟地址转换到主存储地址的页表的第一页表项（PTE）。页表包括与第二页表条目相邻的第二页表条目。基于主存储器的相应页面是连续的，确定第一PTE是否可以与第二PTE连接。在页表中设置用于指示由第一PTE和第二PTE标识的主存储页是连续的标记。

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