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1. 发明授权

US07497696B2 Socket for land grid array package 有权
标题翻译： Socket for Land Grid阵列封装
公开(公告)号：US07497696B2
公开(公告)日：2009-03-03
申请号：US11729581
申请日：2007-03-29
申请人： Robert Martinson , Tieyu Zheng
发明人： Robert Martinson , Tieyu Zheng
IPC分类号： H01R12/00
CPC分类号： H01R13/2442 , H01R43/0249 , H01R43/0256
摘要： A land grid array socket and a microelectronic assembly including the socket. The socket comprises: a housing; an array of through-contacts on the housing; a solder ball standoff element on a PCB side of the housing; and a seating plane standoff element on a package side of the housing, the seating plane standoff element being aligned with the solder ball standoff element to form a loading force support element therewith.
摘要翻译：一种地面栅格阵列插座和一个包括插座的微电子组件。插座包括：壳体; 壳体上的一组通孔; 在壳体的PCB侧上的焊球支架元件; 以及在所述壳体的封装侧上的就座平面间隔元件，所述就座平面支座元件与所述焊球支座元件对齐以与其形成加载力支撑元件。

2. 发明申请

US20080242123A1 Socket for land grid array package 有权
标题翻译： Socket for Land Grid阵列封装
公开(公告)号：US20080242123A1
公开(公告)日：2008-10-02
申请号：US11729581
申请日：2007-03-29
申请人： Robert Martinson , Tieyu Zheng
发明人： Robert Martinson , Tieyu Zheng
IPC分类号： H01R12/00
CPC分类号： H01R13/2442 , H01R43/0249 , H01R43/0256
摘要： A land grid array socket and a microelectronic assembly including the socket. The socket comprises: a housing; an array of through-contacts on the housing; a solder ball standoff element on a PCB side of the housing; and a seating plane standoff element on a package side of the housing, the seating plane standoff element being aligned with the solder ball standoff element to form a loading force support element therewith.
摘要翻译：一种地面栅格阵列插座和一个包括插座的微电子组件。插座包括：壳体; 壳体上的一组通孔; 在壳体的PCB侧上的焊球支架元件; 以及在所述壳体的封装侧上的就座平面间隔元件，所述就座平面支座元件与所述焊球支座元件对齐以与其形成加载力支撑元件。

3. 发明申请

US20150127983A1 TEST, VALIDATION, AND DEBUG ARCHITECTURE 审中-公开
标题翻译：测试，验证和调试架构
公开(公告)号：US20150127983A1
公开(公告)日：2015-05-07
申请号：US13997182
申请日：2010-12-23
申请人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Briar Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
发明人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Briar Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
IPC分类号： G06F11/273
CPC分类号： G06F11/2733 , G06F11/267
摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.
摘要翻译：这里描述了一种用于提供测试，验证和调试架构的装置和方法。在目标或基础级别，硬件（测试设计或DFx）被设计并集成在硅部件中。控制器可以提供对这种钩子的抽象访问，例如通过抽象层来抽象硬件DFx的低级细节。此外，通过接口（如API）的抽象层向更高级的软件/表示层提供服务，例程和数据结构，这些层能够收集测试数据，以便对被测单元/平台进行验证和调试。此外，该架构可能提供对测试架构的分层（多级）安全访问。此外，可以通过使用统一的双向测试访问端口来简化对平台的测试架构的物理访问，同时还可能允许远程访问执行被测部件/平台的远程测试和脱离。本质上描述了一个完整的测试架构栈，用于电子部件，设备和平台的测试，验证和调试。

4. 发明申请

US20090325398A1 Land grid array (LGA) socket with cells and method of fabrication and assembly 有权
标题翻译：带栅格阵列（LGA）插座和电池的制造和组装方法
公开(公告)号：US20090325398A1
公开(公告)日：2009-12-31
申请号：US12215296
申请日：2008-06-25
申请人： Xiaoqing Ma , Tieyu Zheng
发明人： Xiaoqing Ma , Tieyu Zheng
IPC分类号： H01R12/00 , H01R43/00
CPC分类号： H01R12/57 , H01R12/7082 , H01R43/20 , H05K7/1076 , Y10T29/4922
摘要： An LGA socket assembly comprising individual sockets cells, the methods of fabricating and assembling the socket cells into a socket assembly. In an embodiment of the invention, each socket cell comprises an insulative body and a wire. The insulative body is formed around the wire. A first portion of the wire extends from the top surface of the insulative body to form contact tip. A second portion of the wire extends from the bottom surface of the insulative body to form contact paddle. Socket cells are aligned to form a socket assembly.
摘要翻译：包括单个插座单元的LGA插座组件，将插座单元制造并组装到插座组件中的方法。在本发明的一个实施例中，每个插座单元包括绝缘体和导线。绝缘体围绕电线形成。线的第一部分从绝缘体的顶表面延伸以形成接触尖端。线的第二部分从绝缘体的底表面延伸以形成接触片。套筒单元对齐以形成插座组件。

5. 发明授权

US07479015B2 Socket assembly that includes improved contact arrangement 失效
标题翻译：插座组件包括改进的接触布置
公开(公告)号：US07479015B2
公开(公告)日：2009-01-20
申请号：US11427898
申请日：2006-06-30
申请人： Thomas G. Ruttan , Tieyu Zheng
发明人： Thomas G. Ruttan , Tieyu Zheng
IPC分类号： H01R12/00
CPC分类号： H01R12/714 , H01R12/52 , H05K7/1069
摘要： In some embodiments, a socket assembly, electronic assembly and electronic system provide current paths for supplying power and I/O signals to a processor. The socket assembly includes a base having an upper surface and a lower surface with a plurality of contacts extending from the upper surface of the base. Each of the contacts is adjacent to another contact such that each of the contacts is part of a differential pair of contacts. Each of the contacts includes a first side and a second side. One of the contacts in each differential pair of contacts is oriented in one direction while the other contact in each differential pair of contacts is oriented in an opposing direction such that the first side of one of the contacts in each differential pair faces in an opposite direction to the first side of the other contacts in each differential pair.
摘要翻译：在一些实施例中，插座组件，电子组件和电子系统提供用于向处理器提供电力和I / O信号的电流路径。插座组件包括具有上表面的底座和具有从基座的上表面延伸的多个触头的下表面。每个触点与另一个触点相邻，使得每个触点是差动对触点的一部分。每个触点包括第一侧和第二侧。每个差分对触点中的一个触点在一个方向上定向，而每个差动对触点中的另一个触点被定向在相反的方向上，使得每个差分对中的一个触点的第一侧面向相反方向到每个差分对中的其他触点的第一侧。

6. 发明申请

US20050253246A1 Stacked land grid array package 失效
标题翻译：堆叠的土地网格阵列包
公开(公告)号：US20050253246A1
公开(公告)日：2005-11-17
申请号：US10844765
申请日：2004-05-13
申请人： Tieyu Zheng
发明人： Tieyu Zheng
IPC分类号： H01L23/04 , H05K7/10
CPC分类号： H05K7/1053
摘要： A spring plate may be provided between a bolster plate and a board in order to mount components on the opposite side of the board. In some embodiments, the spring plate may provide additional stack tolerance and forceful bias to hold the stack tightly together.
摘要翻译：可以在垫板和板之间设置弹簧板，以便将部件安装在板的相对侧上。在一些实施例中，弹簧板可以提供额外的堆叠公差和有力的偏压以将堆叠紧紧地保持在一起。

7. 发明申请

US20050207458A1 Optoelectronic module with integrated cooler 审中-公开
标题翻译：集成冷却器的光电模块
公开(公告)号：US20050207458A1
公开(公告)日：2005-09-22
申请号：US10805824
申请日：2004-03-22
申请人： Tieyu Zheng
发明人： Tieyu Zheng
IPC分类号： H01S3/04 , H01S5/02 , H01S5/022 , H01S5/024
CPC分类号： H01S5/02415 , H01S5/02212
摘要： An optoelectronic module with integrated cooler is described herein.
摘要翻译：本文描述了具有集成冷却器的光电模块。

8. 发明申请

US20050127281A1 Method and apparatus for manufacturing a transistor-outline (TO) can having a ceramic header 有权
标题翻译：用于制造晶体管轮廓（TO）的方法和装置可以具有陶瓷头
公开(公告)号：US20050127281A1
公开(公告)日：2005-06-16
申请号：US10732938
申请日：2003-12-11
申请人： Tieyu Zheng , Eric Zhinden
发明人： Tieyu Zheng , Eric Zhinden
IPC分类号： G02B6/42 , H01J40/14
CPC分类号： G02B6/4206
摘要： A transponder comprises a first TO having a first insulating base, a photodetector mounted on a first side of the first insulating base, and a metal cap hermetically sealed to the first side of the first insulating base to enclose the photodetector. The transponder also comprises a second TO can having a second insulating base, a light generation device mounted on a first side of the second insulating base, and a metal cap hermetically sealed to the first side of the second insulating base to enclose the light generation device. In one embodiment, the transponder operates at 10 GB/s.
摘要翻译：应答器包括具有第一绝缘基座的第一TO，安装在第一绝缘基座的第一侧上的光电检测器和密封到第一绝缘基座的第一侧以包围光电检测器的金属盖。应答器还包括具有第二绝缘基座的第二TO罐，安装在第二绝缘基座的第一侧上的发光装置和密封到第二绝缘基座的第一侧的金属盖，以封闭光产生装置。在一个实施例中，应答器以10GB / s运行。

9. 发明授权

US10198333B2 Test, validation, and debug architecture 有权
公开(公告)号：US10198333B2
公开(公告)日：2019-02-05
申请号：US13997182
申请日：2010-12-23
申请人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Brian Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
发明人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Brian Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
IPC分类号： G06F11/273 , G06F11/267
摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

10. 发明授权

US07677902B2 Extended package substrate 有权
标题翻译：扩展封装基板
公开(公告)号：US07677902B2
公开(公告)日：2010-03-16
申请号：US11838290
申请日：2007-08-14
申请人： James A. Irvine , Tieyu Zheng
发明人： James A. Irvine , Tieyu Zheng
IPC分类号： H01R12/00
CPC分类号： H01R12/7029 , H01R12/7076 , H01R12/714
摘要： An apparatus may include an integrated circuit package comprising a plurality of conductive pads and having a face, and a socket coupled to the integrated circuit package and to the conductive pads, the socket having a footprint. In some aspects, the footprint is smaller than the face.
摘要翻译：装置可以包括集成电路封装，其包括多个导电焊盘并具有面，以及耦合到集成电路封装件和导电焊盘的插座，插座具有占用面积。在某些方面，占地面积小于面部。

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