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1. 发明申请

US20150127983A1 TEST, VALIDATION, AND DEBUG ARCHITECTURE 审中-公开
标题翻译：测试，验证和调试架构
公开(公告)号：US20150127983A1
公开(公告)日：2015-05-07
申请号：US13997182
申请日：2010-12-23
申请人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Briar Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
发明人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Briar Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
IPC分类号： G06F11/273
CPC分类号： G06F11/2733 , G06F11/267
摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.
摘要翻译：这里描述了一种用于提供测试，验证和调试架构的装置和方法。在目标或基础级别，硬件（测试设计或DFx）被设计并集成在硅部件中。控制器可以提供对这种钩子的抽象访问，例如通过抽象层来抽象硬件DFx的低级细节。此外，通过接口（如API）的抽象层向更高级的软件/表示层提供服务，例程和数据结构，这些层能够收集测试数据，以便对被测单元/平台进行验证和调试。此外，该架构可能提供对测试架构的分层（多级）安全访问。此外，可以通过使用统一的双向测试访问端口来简化对平台的测试架构的物理访问，同时还可能允许远程访问执行被测部件/平台的远程测试和脱离。本质上描述了一个完整的测试架构栈，用于电子部件，设备和平台的测试，验证和调试。

2. 发明授权

US10198333B2 Test, validation, and debug architecture 有权
公开(公告)号：US10198333B2
公开(公告)日：2019-02-05
申请号：US13997182
申请日：2010-12-23
申请人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Brian Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
发明人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Brian Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
IPC分类号： G06F11/273 , G06F11/267
摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

3. 发明授权

US07167876B2 Generalized configurator software system 有权
标题翻译：通用配置软件系统
公开(公告)号：US07167876B2
公开(公告)日：2007-01-23
申请号：US10280282
申请日：2002-10-25
申请人： Ammon Cookson , David C. Florey , Andre C Sublett , Jeffrey J. Kraus
发明人： Ammon Cookson , David C. Florey , Andre C Sublett , Jeffrey J. Kraus
IPC分类号： G06F17/30 , G06F7/00
CPC分类号： G06Q30/0603 , Y10S707/99933 , Y10S707/99943
摘要： A generalized configurator software system provides separate building and executing of software-based configuration definitions from which any of a wide variety of articles may be specified or configured. For example, the configuration definitions may relate to various features or components that may be selected for or incorporated into or used to select or specify any type of article, including a personal computer, an automobile, a construction project (e.g., a bathroom remodel or a multistory structure), etc. The configuration definitions are stored in a definitions database and are built or constructed by a set-up user from a generalized configurator data structure or framework that may include any or all of variables, items, formulas, and assemblies. The variables, items, formulas, and assemblies are specified to represent the generic features or components that may be selected for one or more articles, and also include operating logic for selecting specific ones of the features or components. Accordingly, the configuration definitions define the basis on which a configuring user can select, specify, or “configure” any of one or more articles.
摘要翻译：广义配置软件系统提供单独的构建和执行基于软件的配置定义，可以从其中指定或配置各种各样的文章。例如，配置定义可以涉及可以被选择用于或并入或用于选择或指定任何类型的物品的各种特征或组件，包括个人计算机，汽车，建筑项目（例如，浴室改造或多层结构）等。配置定义存储在定义数据库中，并由建立用户从广义配置器数据结构或框架构建或构建，可以包括变量，项目，公式和程序集中的任何一个或全部。指定变量，项目，公式和程序集来表示可能为一个或多个文章选择的通用特征或组件，还包括用于选择特定特征或组件的操作逻辑。因此，配置定义定义了配置用户可以选择，指定或“配置”一个或多个文章中的任何一个的基础。

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