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1. 发明申请

US20150127983A1 TEST, VALIDATION, AND DEBUG ARCHITECTURE 审中-公开
标题翻译：测试，验证和调试架构
公开(公告)号：US20150127983A1
公开(公告)日：2015-05-07
申请号：US13997182
申请日：2010-12-23
申请人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Briar Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
发明人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Briar Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
IPC分类号： G06F11/273
CPC分类号： G06F11/2733 , G06F11/267
摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.
摘要翻译：这里描述了一种用于提供测试，验证和调试架构的装置和方法。在目标或基础级别，硬件（测试设计或DFx）被设计并集成在硅部件中。控制器可以提供对这种钩子的抽象访问，例如通过抽象层来抽象硬件DFx的低级细节。此外，通过接口（如API）的抽象层向更高级的软件/表示层提供服务，例程和数据结构，这些层能够收集测试数据，以便对被测单元/平台进行验证和调试。此外，该架构可能提供对测试架构的分层（多级）安全访问。此外，可以通过使用统一的双向测试访问端口来简化对平台的测试架构的物理访问，同时还可能允许远程访问执行被测部件/平台的远程测试和脱离。本质上描述了一个完整的测试架构栈，用于电子部件，设备和平台的测试，验证和调试。

2. 发明授权

US10198333B2 Test, validation, and debug architecture 有权
公开(公告)号：US10198333B2
公开(公告)日：2019-02-05
申请号：US13997182
申请日：2010-12-23
申请人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Brian Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
发明人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Brian Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
IPC分类号： G06F11/273 , G06F11/267
摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

3. 发明授权

US07403027B2 Apparatuses and methods for outputting signals during self-heat burn-in modes of operation 有权
标题翻译：在自热老化模式下输出信号的装置和方法
公开(公告)号：US07403027B2
公开(公告)日：2008-07-22
申请号：US11554525
申请日：2006-10-30
申请人： Yuen Tat Lee , Soon Eng Low , Naveendran Balasingam
发明人： Yuen Tat Lee , Soon Eng Low , Naveendran Balasingam
IPC分类号： G01R31/02 , G01R31/28
CPC分类号： G01R31/2875 , G01R31/2856
摘要： An apparatus and method for selecting and outputting test patterns and internal signals during various SHBI modes of operation. The apparatus may include multiple input/output (I/O) pins, one or more functional blocks, a Self-Heat Burn-In (SHBI) state machine that is coupled to the I/O pins and the one or more functional blocks, and a logic selector circuitry that is coupled to the SHBI state machine and the one or more functional blocks. The SHBI state machine may provide to the I/O pins with first one or more test patterns during a first SHBI mode of operation, and to provide the one or more functional blocks with second one or more test patterns during a second SHBI mode of operation. The logic selector circuitry is configured to select and output the first one or more test patterns to stress the I/O pins during the first SHBI mode of operation, and to select and output internal signals of the one more functional blocks during the second SHBI mode of operation.
摘要翻译：一种用于在各种SHBI操作模式下选择和输出测试图案和内部信号的装置和方法。该装置可以包括耦合到I / O引脚和一个或多个功能块的多个输入/输出（I / O）引脚，一个或多个功能块，自热烧伤（SHBI）状态机，以及耦合到所述SHBI状态机和所述一个或多个功能块的逻辑选择器电路。 SHBI状态机可以在第一SHBI操作模式期间以第一个或多个测试模式向I / O引脚提供，并且在第二SHBI操作模式期间向一个或多个功能块提供第二个一个或多个测试模式。逻辑选择器电路被配置为选择和输出第一个或多个测试图案，以在第一SHBI操作模式期间对I / O引脚施加压力，并且在第二SHBI模式期间选择并输出多个功能块的内部信号的操作。

4. 发明申请

US20080100327A1 APPARATUSES AND METHODS FOR OUTPUTTING SIGNALS DURING SELF-HEAT BURN-IN MODES OF OPERATION 有权
标题翻译：自加热输入模式下输出信号的装置和方法
公开(公告)号：US20080100327A1
公开(公告)日：2008-05-01
申请号：US11554525
申请日：2006-10-30
申请人： Yuen Tat Lee , Soon Eng Low , Naveendran Balasingam
发明人： Yuen Tat Lee , Soon Eng Low , Naveendran Balasingam
IPC分类号： G01R31/02
CPC分类号： G01R31/2875 , G01R31/2856
摘要： An apparatus and method for selecting and outputting test patterns and internal signals during various SHBI modes of operation. The apparatus may include multiple input/output (I/O) pins, one or more functional blocks, a Self-Heat Burn-In (SHBI) state machine that is coupled to the I/O pins and the one or more functional blocks, and a logic selector circuitry that is coupled to the SHBI state machine and the one or more functional blocks. The SHBI state machine may provide to the I/O pins with first one or more test patterns during a first SHBI mode of operation, and to provide the one or more functional blocks with second one or more test patterns during a second SHBI mode of operation. The logic selector circuitry is configured to select and output the first one or more test patterns to stress the I/O pins during the first SHBI mode of operation, and to select and output internal signals of the one more functional blocks during the second SHBI mode of operation.
摘要翻译：一种用于在各种SHBI操作模式下选择和输出测试图案和内部信号的装置和方法。该装置可以包括耦合到I / O引脚和一个或多个功能块的多个输入/输出（I / O）引脚，一个或多个功能块，自热烧伤（SHBI）状态机，以及耦合到所述SHBI状态机和所述一个或多个功能块的逻辑选择器电路。 SHBI状态机可以在第一SHBI操作模式期间以第一个或多个测试模式向I / O引脚提供，并且在第二SHBI操作模式期间向一个或多个功能块提供第二个一个或多个测试模式。逻辑选择器电路被配置为选择和输出第一个或多个测试图案，以在第一SHBI操作模式期间对I / O引脚施加压力，并且在第二SHBI模式期间选择并输出多个功能块的内部信号的操作。

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