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1. 发明授权

US6035262A Real time observation serial scan test architecture 失效
标题翻译：实时观察串行扫描测试架构
公开(公告)号：US6035262A
公开(公告)日：2000-03-07
申请号：US266431
申请日：1994-06-27
申请人： Walter E. Gibson , Jeffery A. Sprouse , Eduardo M. Lipiansky , Javad Khakbaz , Michael A. Plum , Philip R. Manela , Ko Yamamoto
发明人： Walter E. Gibson , Jeffery A. Sprouse , Eduardo M. Lipiansky , Javad Khakbaz , Michael A. Plum , Philip R. Manela , Ko Yamamoto
IPC分类号： G01R31/3185 , H03K3/00
CPC分类号： G01R31/318555
摘要： Logic circuitry in the form of an integrated circuit includes a number of scannable registers located at various locations of the logic circuitry to continuously sample signal states thereat. In response to signalling from a maintenance diagnostic processor the scannable registers can be commanded to freeze their content for extraction and observation to determining the operating condition of the logic circuitry.
摘要翻译：集成电路形式的逻辑电路包括位于逻辑电路的不同位置的多个可扫描寄存器，用于连续地采样信号状态。响应于来自维护诊断处理器的信号，可以命令可扫描寄存器冻结其内容以进行提取和观察以确定逻辑电路的操作状态。

2. 发明授权

US5694401A Fault isolation using pseudo-random scan 失效
标题翻译：使用伪随机扫描进行故障隔离
公开(公告)号：US5694401A
公开(公告)日：1997-12-02
申请号：US787452
申请日：1997-01-22
申请人： Walter E. Gibson
发明人： Walter E. Gibson
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318544 , G01R31/318385 , G06F2201/83
摘要： A digital system, comprising a plurality of integrated circuits that are designed to be scannable for pseudo-random scan testing. Testing begins and proceeds in normal binary-tree fashion, subjecting the system to a pseudo-random scan test and developing from that test a signature that is compared to a standard signature. If the comparison is unequal, portions of the system are subjected to pseudo-random scan testing, in normal binary-tree fashion, until the integrated circuit level is reached whereat a final mis-compare for the signature developed for a integrated circuit is obtained. Then, each bit position of the scan for such integrated circuit is classified according to the source of data for its primary input, and pseudo-random scan testing conducted to extract signatures for each such classified source. When a bad signature is reached, after comparing to standard signatures, the fault has been isolated to the classified source.
摘要翻译：一种数字系统，包括被设计为可扫描用于伪随机扫描测试的多个集成电路。测试开始并以正常的二叉树方式进行，使系统进行伪随机扫描测试，并从该测试开发与标准签名进行比较的签名。如果比较不相等，则系统的一部分以正常的二叉树方式进行伪随机扫描测试，直到达到集成电路电平达到集成电路开发的签名的最终错误比较为止。然后，针对这种集成电路的扫描的每个比特位置根据其主要输入的数据源进行分类，并进行伪随机扫描测试以提取每个这样的分类源的签名。当达到不良签名时，与标准签名进行比较后，故障已被隔离到分类来源。

3. 发明授权

US5450455A Method and apparatus for including the states of nonscannable parts in a scan chain 失效
标题翻译：用于在扫描链中包括不可取消部分的状态的方法和装置
公开(公告)号：US5450455A
公开(公告)日：1995-09-12
申请号：US84039
申请日：1993-06-28
申请人： Stephen W. Hamilton , Walter E. Gibson , Cheng-Gang Kong
发明人： Stephen W. Hamilton , Walter E. Gibson , Cheng-Gang Kong
IPC分类号： G06F11/22 , G01R31/3185 , H04B3/46
CPC分类号： G01R31/318586
摘要： A scannable logic unit includes one or more storage registers that maintain copies of data communicated from the scannable unit to registers in a nonscannable unit. When the scannable unit is subjected to a scan test, the registers will contain state information respecting that transfer to the nonscannable unit. When the scannable and nonscannable units are placed in a run condition, the registers supply to the nonscannable unit state information for continuing operation.
摘要翻译：可扫描逻辑单元包括一个或多个存储寄存器，其将从可扫描单元传送的数据的副本维护到非可更新单元中的寄存器。当可扫描单元进行扫描测试时，寄存器将包含关于转移到不可更改单元的状态信息。当可扫描和不可取消单元处于运行状态时，寄存器提供用于继续操作的非可修改单元状态信息。

4. 发明授权

US6029263A Interconnect testing using non-compatible scan architectures 失效
标题翻译：使用不兼容的扫描架构进行互连测试
公开(公告)号：US6029263A
公开(公告)日：2000-02-22
申请号：US268370
申请日：1994-06-30
申请人： Walter E. Gibson
发明人： Walter E. Gibson
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318586
摘要： A method is provided that provides a test of an interconnect that communicates information between two digital circuits. One of the digital circuits is constructed to be "scannable" so that it at least includes scannable registers capable of applying signals to, and sampling signals at, the interconnect. The other digital circuit has a different scan architecture such as, for example, that specified by IEEE Standard 1149.1. The method allows the interconnect between the two digital circuits, each having scan architecture that is not compatible with that of the other, to be tested.
摘要翻译：提供一种提供在两个数字电路之间传送信息的互连测试的方法。数字电路中的一个被构造为“可扫描”，使得其至少包括能够在互连处施加信号和对信号进行采样的可扫描寄存器。另一数字电路具有不同的扫描架构，例如由IEEE标准1149.1规定的扫描架构。该方法允许测试两个数字电路之间的互连，每个数字电路具有与另一个不兼容的扫描架构。

5. 发明授权

US5951703A System and method for performing improved pseudo-random testing of systems having multi driver buses 失效
标题翻译：用于执行具有多个驱动器总线的系统的改进的伪随机测试的系统和方法
公开(公告)号：US5951703A
公开(公告)日：1999-09-14
申请号：US083419
申请日：1993-06-28
申请人： Jeffrey A. Sprouse , Walter E. Gibson
发明人： Jeffrey A. Sprouse , Walter E. Gibson
IPC分类号： G06F11/22 , G01R31/3185 , G06F11/267 , G06F11/27 , G06F13/00 , G06F13/36 , G01R31/28
CPC分类号： G06F11/2221 , G01R31/318385 , G01R31/318555 , G06F11/27
摘要： A digital system includes a number of digital subsystems interconnected by a shared bus structure that is mutually exclusively accessible for communicating data between the subsystems. The system is structured to be tested by pseudo-random scan test methodology. Each subsystem includes a counter that, during scan test periods, provides an enable signal to the bus access or driver circuitry of the associated subsystem. A scan test operation is preceded by pre-loading each counter with a predetermined state so that, initially, and throughout the test period, one and only one digital subsystem will drive the shared data bus. Each scan sequence (comprising a scan in, an execution cycle, and a scan out of the pseudo-random test strings) will result in the counters being clocked once so that a new subsystem will be enable to drive the bus the next sequence, permitting the bus access circuitry of each subsystem, and the bus itself, to be tested.
摘要翻译：数字系统包括通过共享总线结构互连的多个数字子系统，该共享总线结构相互独占可访问以在子系统之间传送数据。该系统的结构是通过伪随机扫描测试方法进行测试。每个子系统包括一个计数器，在扫描测试期间，向相关子系统的总线访问或驱动器电路提供使能信号。在扫描测试操作之前，以预定状态预加载每个计数器，使得最初和整个测试周期中，只有一个数字子系统将驱动共享数据总线。每个扫描序列（包括扫描，执行周期和伪随机测试字符串中的扫描）将导致计数器被计时一次，以便新的子系统将能够驱动总线下一个序列，从而允许每个子系统的总线访问电路和总线本身进行测试。

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