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1. 发明授权

US06959364B2 Partially inclusive snoop filter 失效
标题翻译：部分包围窥探过滤器
公开(公告)号：US06959364B2
公开(公告)日：2005-10-25
申请号：US10186490
申请日：2002-06-28
申请人： Robert J. Safranek , Kai Cheng
发明人： Robert J. Safranek , Kai Cheng
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/082 , G06F12/0813 , G06F12/0831 , G06F2212/2542
摘要： In some embodiments, the invention includes a snoop filter, wherein entries in the snoop filter are allocated in response to initial accesses of local cache lines by a remote node, but entries in the snoop filter are not allocated in response to accesses of the local cache lines by a local node. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，本发明包括窥探过滤器，其中响应于远程节点对本地高速缓存行的初始访问来分配窥探过滤器中的条目，但是响应于本地高速缓存的访问不会分配窥探过滤器中的条目线路由本地节点。描述和要求保护其他实施例。

2. 发明授权

US09405646B2 Method and apparatus for injecting errors into memory 有权
标题翻译：将错误注入存储器的方法和装置
公开(公告)号：US09405646B2
公开(公告)日：2016-08-02
申请号：US13992506
申请日：2011-09-29
申请人： Theodros Yigzaw , Kai Cheng , Mohan J. Kumar , Jose A. Vargas , Gopikrishna Jandhyala
发明人： Theodros Yigzaw , Kai Cheng , Mohan J. Kumar , Jose A. Vargas , Gopikrishna Jandhyala
IPC分类号： G06F11/00 , G06F11/263 , G06F11/36
CPC分类号： G06F11/263 , G06F11/3664 , G06F11/3688
摘要： Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.
摘要翻译：公开了一种向存储器注入错误的装置和方法。在一个实施例中，专用接口包括错误注入系统地址寄存器和耦合到错误注入系统地址寄存器的错误注入掩模寄存器。如果错误注入系统地址寄存器包含与输入写入地址匹配的系统地址，则错误注入掩码寄存器会向存储器输出错误。

3. 发明申请

US20150220410A1 MECHANISM FOR ACHIEVING HIGH MEMORY RELIABLITY, AVAILABILITY AND SERVICEABILITY 审中-公开
标题翻译：实现高记忆可靠性，可用性和可维护性的机制
公开(公告)号：US20150220410A1
公开(公告)日：2015-08-06
申请号：US14563761
申请日：2014-12-08
申请人： DABLEENA DAS , Kai Cheng , Jonathan C. Jasper
发明人： DABLEENA DAS , Kai Cheng , Jonathan C. Jasper
IPC分类号： G06F11/20 , G06F11/10
CPC分类号： G06F11/2094 , G06F11/1044 , G06F11/1076 , H03M13/05
摘要： A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.
摘要翻译：描述了根据本发明的一个实施例的用于实现高存储器可靠性，可用性和可服务性（RAS）的机制。本发明的实施例的方法包括：检测在计算系统处的存储器系统的第一通道的多个存储器件的第一存储器件的永久故障，并通过合并第一纠错码来消除第一故障（ ECC）具有第二信道的第二ECC定位器装置的第一信道的定位装置，其中在第二信道执行合并。

4. 发明申请

US20150058524A1 BIMODAL FUNCTIONALITY BETWEEN COHERENT LINK AND MEMORY EXPANSION 审中-公开
标题翻译：相关链接和内存扩展之间的双向功能
公开(公告)号：US20150058524A1
公开(公告)日：2015-02-26
申请号：US13808314
申请日：2012-01-04
申请人： Kenneth C. Creta , Jason W. Horihan , Robert G. Blankenship , Kai Cheng
发明人： Kenneth C. Creta , Jason W. Horihan , Robert G. Blankenship , Kai Cheng
IPC分类号： G06F3/06 , G11C13/00 , G11C14/00
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0679 , G06F13/16 , G06F13/4234 , G06F2206/1014 , G11C13/0002 , G11C14/009
摘要： Methods and apparatus relating to provide bimodal functionality between a coherent link and memory expansion are described. In one embodiment, a processor is coupled to one or more agents via a coherent interconnect. The processor is also coupled to one or more Dual Inline Memory Modules (DIMMs) via a link logic. The logic supports read or write commands directed at the one or more DIMMs based on a single bit of data. Other embodiments are also disclosed and claimed.
摘要翻译：描述了在相干链路和存储器扩展之间提供双模功能相关的方法和装置。在一个实施例中，处理器经由相干互连耦合到一个或多个代理。处理器还通过链路逻辑耦合到一个或多个双列直插式内存模块（DIMM）。该逻辑支持基于单个数据位读取或写入指向一个或多个DIMM的命令。还公开并要求保护其他实施例。

5. 发明授权

US08914704B2 Mechanism for achieving high memory reliablity, availability and serviceability 有权
标题翻译：实现高内存可靠性，可用性和可维护性的机制
公开(公告)号：US08914704B2
公开(公告)日：2014-12-16
申请号：US13538922
申请日：2012-06-29
申请人： Debaleena Das , Kai Cheng , Jonathan C. Jasper
发明人： Debaleena Das , Kai Cheng , Jonathan C. Jasper
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/2094 , G06F11/1044 , G06F11/1076 , H03M13/05
摘要： A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.
摘要翻译：描述了根据本发明的一个实施例的用于实现高存储器可靠性，可用性和可服务性（RAS）的机制。本发明的实施例的方法包括：检测在计算系统处的存储器系统的第一通道的多个存储器件的第一存储器件的永久故障，并通过合并第一纠错码来消除第一故障（ ECC）具有第二信道的第二ECC定位器装置的第一信道的定位装置，其中在第二信道执行合并。

6. 发明申请

US20120317328A1 SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEM 有权
标题翻译：可分配的分布式存储器和I / O多处理器系统
公开(公告)号：US20120317328A1
公开(公告)日：2012-12-13
申请号：US13590936
申请日：2012-08-21
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

7. 发明申请

US20120057163A1 METHOD FOR FORMING A NANOSTRUCTURE PENETRATING A LAYER 有权
标题翻译：形成一层纳米结构的方法
公开(公告)号：US20120057163A1
公开(公告)日：2012-03-08
申请号：US13157154
申请日：2011-06-09
申请人： Kai Cheng , Pol Van Dorpe , Liesbet Lagae , Gustaaf Borghs , Chang Chen
发明人： Kai Cheng , Pol Van Dorpe , Liesbet Lagae , Gustaaf Borghs , Chang Chen
IPC分类号： H01L31/00 , H01L31/18 , G01N21/55 , B82Y40/00 , B82Y99/00
CPC分类号： B82Y15/00 , B82Y20/00 , B82Y40/00 , G01N21/554 , G01N21/648 , G01N21/658 , G01N33/48721 , G01N2021/653 , Y10S977/724 , Y10S977/924
摘要： A method for forming a nanostructure penetrating a layer and the device made thereof is disclosed. In one aspect, the device has a substrate, a layer present thereon, and a nanostructure penetrating the layer. The nanostructure defines a nanoscale passageway through which a molecule to be analyzed can pass through. The nanostructure has, in cross-sectional view, a substantially triangular shape. This shape is particularly achieved by growth of an epitaxial layer having crystal facets defining tilted sidewalls of the nanostructure. It is highly suitably for use for optical characterization of molecular structure, particularly with surface plasmon enhanced transmission spectroscopy.
摘要翻译：公开了一种形成穿透层的纳米结构的方法及其制造的器件。在一个方面，该装置具有基底，存在于其上的层和穿透该层的纳米结构。纳米结构定义了一个纳米尺度的通道，待分析的分子通过该通道通过。纳米结构在横截面图中具有基本上三角形的形状。通过具有限定纳米结构的倾斜侧壁的晶面的外延层的生长，特别地实现了该形状。它非常适合用于分子结构的光学表征，特别是用于表面等离子体增强透射光谱。

8. 发明授权

US07996625B2 Method and apparatus for reducing memory latency in a cache coherent multi-node architecture 有权
标题翻译：用于减少高速缓存一致多节点架构中的存储器延迟的方法和装置
公开(公告)号：US07996625B2
公开(公告)日：2011-08-09
申请号：US11790989
申请日：2007-04-30
申请人： Manoj Khare , Faye A. Briggs , Akhilesh Kumar , Lily P. Looi , Kai Cheng
发明人： Manoj Khare , Faye A. Briggs , Akhilesh Kumar , Lily P. Looi , Kai Cheng
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0817 , G06F12/0862 , G06F2212/2542 , G06F2212/507
摘要： A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.
摘要翻译：一种用于减少多节点架构中的存储器延迟的方法。在一个实施例中，在确定高速缓存一致性协议的结果之前，向家庭节点发出推测性读请求。家庭节点启动对存储器的读取以完成推测性读取请求。高速缓存一致性协议的结果可以由相干代理确定，以在发布推测读请求之后解析高速缓存一致性。

9. 发明授权

US07991963B2 In-memory, in-page directory cache coherency scheme 有权
标题翻译：内存中，页内目录缓存一致性方案
公开(公告)号：US07991963B2
公开(公告)日：2011-08-02
申请号：US12006326
申请日：2007-12-31
申请人： Ian M. Steiner , Zhong-Ning George Cai , Saurabh Tiwari , Kai Cheng
发明人： Ian M. Steiner , Zhong-Ning George Cai , Saurabh Tiwari , Kai Cheng
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： In an embodiment, the method provides receiving a memory access request for a demanded cache line from a processor of a plurality of processors; accessing coherency information associated with the demanded cache line from a memory unit by bringing in from a memory page in which the demanded cache line is stored, the memory page also including a directory line having coherency information corresponding to the demanded cache line; reading data associated with the demanded cache line in accordance with the coherency information; and returning the data to the processor.
摘要翻译：在一个实施例中，该方法提供从多个处理器的处理器接收对所请求的高速缓存行的存储器访问请求; 通过从其中存储所请求的高速缓存线的存储器页引入来存储与所请求的高速缓存行相关联的一致性信息，所述存储器页面还包括具有与所请求的高速缓存行对应的一致性信息的目录行; 根据一致性信息读取与所请求的高速缓存线相关联的数据; 并将数据返回到处理器。

10. 发明申请

US20110101370A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110101370A1
公开(公告)日：2011-05-05
申请号：US12916346
申请日：2010-10-29
申请人： Kai Cheng , Stefan Degroote
发明人： Kai Cheng , Stefan Degroote
IPC分类号： H01L29/66 , H01L21/20
CPC分类号： H01L21/02389 , H01L21/02422 , H01L21/0245 , H01L21/02458 , H01L21/0254 , H01L21/02639 , H01L29/0649 , H01L29/2003 , H01L29/66477 , H01L29/7786
摘要： A semiconductor device and method of manufacturing the device is disclosed. In one aspect, the device includes a semiconductor substrate and a GaN-type layer stack on top of the semiconductor substrate. The GaN-type layer stack has at least one buffer layer, a first active layer and a second active layer. Active device regions are definable at an interface of the first and second active layer. The semiconductor substrate is present on an insulating layer and is patterned to define trenches according to a predefined pattern, which includes at least one trench underlying the active device region. The trenches extend from the insulating layer into at least one buffer layer of the GaN-type layer stack and are overgrown within the at least one buffer layer, so as to obtain that the first and the second active layer are continuous at least within the active device regions.
摘要翻译：公开了一种半导体器件及其制造方法。一方面，该器件在半导体衬底的顶部上包括半导体衬底和GaN型层叠层。 GaN型层堆叠具有至少一个缓冲层，第一有源层和第二有源层。有源器件区可以在第一和第二有源层的界面处被定义。半导体衬底存在于绝缘层上，并被图案化以根据预定图案限定沟槽，其包括位于有源器件区域下方的至少一个沟槽。沟槽从绝缘层延伸到GaN型层堆叠的至少一个缓冲层中，并且在至少一个缓冲层内长满，从而获得第一和第二活性层至少在活性物质内连续设备区域。

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