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    • 4. 发明申请
    • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF
    • 半导体器件及其制造方法
    • US20110101370A1
    • 2011-05-05
    • US12916346
    • 2010-10-29
    • Kai ChengStefan Degroote
    • Kai ChengStefan Degroote
    • H01L29/66H01L21/20
    • H01L21/02389H01L21/02422H01L21/0245H01L21/02458H01L21/0254H01L21/02639H01L29/0649H01L29/2003H01L29/66477H01L29/7786
    • A semiconductor device and method of manufacturing the device is disclosed. In one aspect, the device includes a semiconductor substrate and a GaN-type layer stack on top of the semiconductor substrate. The GaN-type layer stack has at least one buffer layer, a first active layer and a second active layer. Active device regions are definable at an interface of the first and second active layer. The semiconductor substrate is present on an insulating layer and is patterned to define trenches according to a predefined pattern, which includes at least one trench underlying the active device region. The trenches extend from the insulating layer into at least one buffer layer of the GaN-type layer stack and are overgrown within the at least one buffer layer, so as to obtain that the first and the second active layer are continuous at least within the active device regions.
    • 公开了一种半导体器件及其制造方法。 一方面,该器件在半导体衬底的顶部上包​​括半导体衬底和GaN型层叠层。 GaN型层堆叠具有至少一个缓冲层,第一有源层和第二有源层。 有源器件区可以在第一和第二有源层的界面处被定义。 半导体衬底存在于绝缘层上,并被图案化以根据预定图案限定沟槽,其包括位于有源器件区域下方的至少一个沟槽。 沟槽从绝缘层延伸到GaN型层堆叠的至少一个缓冲层中,并且在至少一个缓冲层内长满,从而获得第一和第二活性层至少在活性物质内连续 设备区域。
    • 5. 发明授权
    • Semiconductor device and method of manufacturing thereof
    • 半导体装置及其制造方法
    • US08373204B2
    • 2013-02-12
    • US12916346
    • 2010-10-29
    • Kai ChengStefan Degroote
    • Kai ChengStefan Degroote
    • H01L27/148
    • H01L21/02389H01L21/02422H01L21/0245H01L21/02458H01L21/0254H01L21/02639H01L29/0649H01L29/2003H01L29/66477H01L29/7786
    • A semiconductor device and method of manufacturing the device is disclosed. In one aspect, the device includes a semiconductor substrate and a GaN-type layer stack on top of the semiconductor substrate. The GaN-type layer stack has at least one buffer layer, a first active layer and a second active layer. Active device regions are definable at an interface of the first and second active layer. The semiconductor substrate is present on an insulating layer and is patterned to define trenches according to a predefined pattern, which includes at least one trench underlying the active device region. The trenches extend from the insulating layer into at least one buffer layer of the GaN-type layer stack and are overgrown within the at least one buffer layer, so as to obtain that the first and the second active layer are continuous at least within the active device regions.
    • 公开了一种半导体器件及其制造方法。 一方面,该器件在半导体衬底的顶部上包​​括半导体衬底和GaN型层叠层。 GaN型层堆叠具有至少一个缓冲层,第一有源层和第二有源层。 有源器件区可以在第一和第二有源层的界面处被定义。 半导体衬底存在于绝缘层上,并被图案化以根据预定图案限定沟槽,其包括位于有源器件区域下方的至少一个沟槽。 沟槽从绝缘层延伸到GaN型层堆叠的至少一个缓冲层中,并且在至少一个缓冲层内长满,以便获得第一和第二活性层至少在活性物质内连续 设备区域。
    • 9. 发明授权
    • Scalable distributed memory and I/O multiprocessor system
    • 可扩展分布式内存和I / O多处理器系统
    • US08745306B2
    • 2014-06-03
    • US13590936
    • 2012-08-21
    • Linda J. RankinPaul R. PierceGregory E. DermerWen-Hann WangKai ChengRichard H. HofsheierNitin Y. Borkar
    • Linda J. RankinPaul R. PierceGregory E. DermerWen-Hann WangKai ChengRichard H. HofsheierNitin Y. Borkar
    • G06F13/00
    • G06F13/4022G06F13/4027
    • A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
    • 多处理器系统包括至少一个处理模块,至少一个I / O模块和互连网络,以将所述至少一个处理模块与所述至少一个输入/输出模块连接。 在示例实施例中,互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。 互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。 使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。 标准处理模块硬件可以与互连网络一起使用,而无需修改BIOS或操作系统。 此外,使用本发明的实施例的互连网络对于处理器主板是非侵入性的。 处理器内存总线,时钟和复位逻辑都保持不变。
    • 10. 发明授权
    • Method of manufacturing a light emitting diode
    • 制造发光二极管的方法
    • US08623685B2
    • 2014-01-07
    • US13092854
    • 2011-04-22
    • Kai Cheng
    • Kai Cheng
    • H01L33/00
    • H01L33/007H01L21/0254H01L21/0262H01L21/02639H01L21/0265H01L33/0079H01L33/12H01L33/20H01L2933/0083
    • A method of manufacturing a light emitting diode is disclosed. In one aspect, the light emitting diode has a carrier, an active layer structure of III-nitride type materials, and a photonic crystal structure of III-nitride type materials. The active layer structure includes a first active layer with an n-type doped layer and a p-type doped layer and suitably a quantum well structure. The photonic crystal structure includes periodically distributed trenches or periodically distributed pillars spaced by one or more trenches. The photonic crystal structure includes an overgrowth layer within which a diameter of a trench gradually increases, and a directional photonic crystal layer in which the diameter of a trench is substantially constant. The diode may be formed in a method wherein the directional photonic crystal layer is provided on a three-dimensional pattern that exposes selected areas of the first surface of the substrate.
    • 公开了一种制造发光二极管的方法。 一方面,发光二极管具有载流子,III族氮化物型材料的有源层结构和III族氮化物型材料的光子晶体结构。 有源层结构包括具有n型掺杂层和p型掺杂层的第一有源层,并且适当地为量子阱结构。 光子晶体结构包括由一个或多个沟槽隔开的周期性分布的沟槽或周期性分布的柱。 光子晶体结构包括其中沟槽直径逐渐增加的过度生长层,以及沟槽直径基本上恒定的定向光子晶体层。 二极管可以以一种方法形成,其中定向光子晶体层设置在暴露基板的第一表面的选定区域的三维图案上。