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    • 7. 发明授权
    • Gate dielectric breakdown protection during ESD events
    • ESD事件期间的栅极绝缘击穿保护
    • US08634174B2
    • 2014-01-21
    • US13115492
    • 2011-05-25
    • Michel J. Abou-KhalilJames P. Di SarroRobert J. Gauthier, Jr.Junjun LiSouvick MitraYang Yang
    • Michel J. Abou-KhalilJames P. Di SarroRobert J. Gauthier, Jr.Junjun LiSouvick MitraYang Yang
    • H02H9/00H02H3/22
    • H02H9/046G06F17/5063H01L27/0285
    • Protection circuits, design structures, and methods for isolating the gate and gate dielectric of a field-effect transistor from electrostatic discharge (ESD). A protection field-effect transistor is located between a protected field-effect transistor and a voltage rail. Under normal operating conditions, the protection field-effect transistor is saturated so that the protected field-effect transistor is coupled to the voltage rail. The protection field-effect transistor may be driven into a cutoff condition in response to an ESD event while the chip is unpowered, which increases the series resistance of an ESD current path between the gate of the protected field-effect transistor and the voltage rail. The voltage drop across the protection field-effect transistor may reduce the ESD stress on the gate dielectric of the protected field-effect transistor. Alternatively, the gate and source of an existing field-effect transistor are selectively coupled provide ESD isolation to the protected field-effect transistor.
    • 用于将场效应晶体管的栅极和栅极电介质与静电放电(ESD)隔离的保护电路,设计结构和方法。 保护场效应晶体管位于受保护的场效应晶体管和电压轨之间。 在正常工作条件下,保护场效应晶体管饱和,使受保护的场效应晶体管耦合到电压轨。 保护场效应晶体管可以在芯片无电源时响应于ESD事件而被驱动成截止状态,这增加了受保护的场效应晶体管的栅极与电压轨之间的ESD电流路径的串联电阻。 保护场效应晶体管两端的电压降可以降低受保护的场效应晶体管的栅极电介质上的ESD应力。 或者,现有的场效应晶体管的栅极和源极被选择性地耦合到提供ESD隔离到受保护的场效应晶体管。