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1. 发明授权

US06651229B2 Generation of refined switching windows in static timing analysis 有权
标题翻译：在静态时序分析中生成精细的切换窗口
公开(公告)号：US06651229B2
公开(公告)日：2003-11-18
申请号：US09682707
申请日：2001-10-09
申请人： Robert J. Allen , Ravishankar Arunachalam , David J. Hathaway
发明人： Robert J. Allen , Ravishankar Arunachalam , David J. Hathaway
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： A method and structure to determine timing windows in a static timing analysis of an integrated circuit design, determines for at least one node in the integrated circuit design, an initial set of sub-windows and merges the sub-windows of the initial set into a final set of sub-windows.
摘要翻译：在集成电路设计的静态时序分析中确定定时窗口的方法和结构，为集成电路设计中的至少一个节点确定初始的子窗口集合并将初始集合的子窗口合并为最后一套子窗口。

2. 发明授权

US06988255B2 Generation of refined switching windows in static timing analysis 失效
公开(公告)号：US06988255B2
公开(公告)日：2006-01-17
申请号：US10667083
申请日：2003-09-18
申请人： Robert J. Allen , Ravishankar Arunachalam , David J. Hathaway
发明人： Robert J. Allen , Ravishankar Arunachalam , David J. Hathaway
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and structure to determine timing windows in a static timing analysis of an integrated circuit design, determines for at least one node in the integrated circuit design, an initial set of sub-windows and merges the sub-windows of the initial set into a final set of sub-windows.

3. 发明授权

US06751744B1 Method of integrated circuit design checking using progressive individual network analysis 有权
标题翻译：集成电路设计检查方法采用渐进式单独网络分析
公开(公告)号：US06751744B1
公开(公告)日：2004-06-15
申请号：US09475799
申请日：1999-12-30
申请人： Robert J. Allen , John M. Cohn , David J. Hathaway
发明人： Robert J. Allen , John M. Cohn , David J. Hathaway
IPC分类号： G06F112
CPC分类号： G06F17/504 , G06F2217/78
摘要： A method for checking integrated circuit designs comprising the steps of calculating a first performance parameter by analyzing the network's sensitivity to a signal applied to the network; comparing the first performance parameter to one or more rules to determine a first pass condition and writing the value of first performance parameter to a netlist file in response to a pass to the first pass condition; followed by calculating a second performance parameter based on a first network model to determine a second pass condition in response to a fail to said first pass condition and writing the second performance parameter to the netlist file in response to a pass to said second pass condition or writing an error flag to the netlist file in response to a fail to said second pass condition is disclosed. The method, at each step, decides if a quick to calculate parameter provides sufficient design margin or if a more accurate but longer to calculate parameter is required.
摘要翻译：一种用于检查集成电路设计的方法，包括以下步骤：通过分析网络对施加到网络的信号的灵敏度来计算第一性能参数; 将所述第一性能参数与一个或多个规则进行比较以确定第一通过条件，并响应于所述第一通过条件的传递将所述第一性能参数的值写入网表文件; 随后基于第一网络模型计算第二性能参数，以响应于所述第一通过条件的失败来确定第二通过条件，并响应于所述第二通过条件的通过将所述第二性能参数写入所述网表文件，或公开了响应于所述第二通过条件的失败向网表文件写入错误标志。该方法在每个步骤中决定快速计算参数是否提供足够的设计余量，或者是否需要更准确但更长的计算参数。

4. 发明申请

US20110262344A1 Catalyst for electrochemical reduction of oxygen 有权
公开(公告)号：US20110262344A1
公开(公告)日：2011-10-27
申请号：US12931366
申请日：2011-01-31
申请人： Andrea F. Gilla , Robert J. Allen
发明人： Andrea F. Gilla , Robert J. Allen
IPC分类号： C01G55/00
CPC分类号： C25B11/04 , C25B1/26 , H01M4/8605 , H01M4/923 , H01M4/926 , Y02P20/129 , Y02P20/20
摘要： The invention relates to a sulphide catalyst for electrochemical reduction of oxygen particularly stable in chemically aggressive environments such as chlorinated hydrochloric acid. The catalyst of the invention comprises a noble metal sulphide single crystalline phase supported on a conductive carbon essentially free of zerovalent metal and of metal oxide phases, obtainable by reduction of metal precursor salts and thio-precursors with a borohydride or other strong reducing agent.

5. 发明授权

US07960520B2 Conversion of lignocellulosic biomass to chemicals and fuels 失效
标题翻译：将木质纤维素生物质转化为化学品和燃料
公开(公告)号：US07960520B2
公开(公告)日：2011-06-14
申请号：US11763538
申请日：2007-06-15
申请人： Michael J. McCall , Robert J. Allen , David E. Mackowiak
发明人： Michael J. McCall , Robert J. Allen , David E. Mackowiak
IPC分类号： C07G1/00 , C08H7/00 , C08L97/00 , D21C11/00 , D21C9/10
CPC分类号： C10L5/44 , C10G1/083 , C10G1/086 , Y02E50/10 , Y02E50/30 , Y02P30/20
摘要： A method for preparing biomass for slurry processing. The method includes solubilizing the solid material into either a dissolved state or a suspended solid in a liquid phase, and treating the liquid phase to produce chemicals and fuels.
摘要翻译：一种用于制备浆料处理生物质的方法。该方法包括将固体物质溶解在溶解状态或液相中的悬浮固体，以及处理液相以产生化学品和燃料。

6. 发明授权

US07752589B2 Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design 失效
标题翻译：用于显示和修改集成电路设计的关键区域的方法，装置和计算机程序产品
公开(公告)号：US07752589B2
公开(公告)日：2010-07-06
申请号：US11620059
申请日：2007-01-05
申请人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.
摘要翻译：一种用于可视地指示有助于定义的关键区域图案的设计的一个或多个边缘之间的交互的方法，装置和计算机程序产品。

7. 发明授权

US07503020B2 IC layout optimization to improve yield 失效
标题翻译： IC布局优化提高产量
公开(公告)号：US07503020B2
公开(公告)日：2009-03-10
申请号：US11424922
申请日：2006-06-19
申请人： Robert J. Allen , Faye D. Baker , Albert M. Chu , Michael S. Gray , Jason Hibbeler , Daniel N. Maynard , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Faye D. Baker , Albert M. Chu , Michael S. Gray , Jason Hibbeler , Daniel N. Maynard , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.
摘要翻译：一种用于优化集成电路设计以提高制造产量的方法和服务。本发明使用制造数据和算法来识别故障概率高的区域，即关键区域。本发明进一步改变电路设计的布局以减少临界面积，从而降低在制造过程中发生故障的可能性。确定关键区域的方法包括通用运行，几何映射和Voronoi图。优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。

8. 发明授权

US07433302B2 Ethernet network implementing redundancy using a single category 5 cable 有权
标题翻译：以太网使用单一类别5电缆实现冗余
公开(公告)号：US07433302B2
公开(公告)日：2008-10-07
申请号：US11123325
申请日：2005-05-04
申请人： Robert J. Allen
发明人： Robert J. Allen
IPC分类号： H04J3/02 , G06F15/16
CPC分类号： H04L12/40182 , H04L12/437 , Y10S370/908 , Y10S370/91
摘要： A method for providing redundancy in a daisy chain local area network employing Category 5 cabling for connecting network devices uses the normally unused twisted wire pairs in the single Cat 5 cable connecting adjacent network devices. The method includes forming in each network device a passive signal path connecting pins of an upstream port associated with the normally unused twisted wire pairs of the Cat 5 cable to pins of a downstream port associated with the normally unused twisted wire pairs of the Cat 5 cable, forming loop back connections at the terminal network devices where the loop back connections connect the normally used twisted wire pairs to the normally unused twisted wire pairs of the Cat 5 cable connected to the terminal network devices, and implementing a Spanning Tree Protocol in each of the network devices for defining an active signal path through the local area network.
摘要翻译：在连接网络设备的采用5类布线的菊花链局域网中提供冗余的方法使用连接相邻网络设备的单个Cat 5电缆中通常使用的双绞线对。该方法包括在每个网络设备中形成被动信号路径，该无源信号路径将与Cat5电缆的通常未使用的双绞线相关联的上游端口的引脚连接到与Cat 5电缆的通常未使用的双绞线对相关联的下游端口的引脚在终端网络设备处形成环回连接，其中环回连接将常用的双绞线连接到连接到终端网络设备的Cat 5电缆的通常使用的双绞线对，并且在每个终端网络设备中实现生成树协议用于定义通过局域网的活动信号路径的网络设备。

9. 发明授权

US07404159B2 Critical area computation of composite fault mechanisms using Voronoi diagrams 有权
标题翻译：使用Voronoi图的复合故障机制的关键区域计算
公开(公告)号：US07404159B2
公开(公告)日：2008-07-22
申请号：US11538913
申请日：2006-10-05
申请人： Robert J. Allen , Evanthia Papadopoulou , Mervyn Yee-Min Tan
发明人： Robert J. Allen , Evanthia Papadopoulou , Mervyn Yee-Min Tan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes the critical area for composite fault mechanisms of the integrated circuit design based on the composite Voronoi diagram.
摘要翻译：公开了一种在集成电路设计中确定与不同类型的故障机制相关联的关键区域的方法。本发明通过为单个故障机制的关键区域构建单独的Voronoi图和基于各个Voronoi图的复合Voronoi图来实现。本发明基于复合Voronoi图计算了集成电路设计复合故障机理的关键区域。

10. 发明申请

US20080121520A1 Carbon-supported metal sulphide catalyst for electrochemical oxygen reduction 有权
标题翻译：用于电化学氧还原的碳载金属硫化物催化剂
公开(公告)号：US20080121520A1
公开(公告)日：2008-05-29
申请号：US11982799
申请日：2007-11-05
申请人： Andrea F. Gulla , Robert J. Allen
发明人： Andrea F. Gulla , Robert J. Allen
IPC分类号： C25B11/04 , B01J27/02
CPC分类号： C25B11/0447 , B01J21/18 , B01J27/045 , H01M4/90 , H01M4/9083 , H01M4/923 , H01M4/926 , Y02E60/50
摘要： An improved carbon supported-noble metal sulphide electrocatalyst suitable for being incorporated in gas-diffusion electrode structures, in particular in oxygen-reducing gas diffusion cathodes for aqueous hydrochloric acid electrolysis. The noble metal sulphide particles are monodispersed on the active carbon particles and the surface area ratio of noble metal sulphide particles to active carbon particles is at least 0.20.
摘要翻译：一种改进的碳负载型贵金属硫化物电催化剂，适用于掺入气体扩散电极结构中，特别是用于盐酸电解盐水的减氧气体扩散阴极中。贵金属硫化物颗粒单分散在活性炭颗粒上，贵金属硫化物颗粒与活性炭颗粒的表面积比至少为0.20。

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