专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070294648A1 IC Layout Optimization To Improve Yield 失效
标题翻译： IC布局优化提高产量
公开(公告)号：US20070294648A1
公开(公告)日：2007-12-20
申请号：US11424922
申请日：2006-06-19
申请人： Robert J. Allen , Faye D. Baker , Albert M. Chu , Michael S. Gray , Jason Hibbeler , Daniel N. Maynard , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Faye D. Baker , Albert M. Chu , Michael S. Gray , Jason Hibbeler , Daniel N. Maynard , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.
摘要翻译：一种用于优化集成电路设计以提高制造产量的方法和服务。本发明使用制造数据和算法来识别故障概率高的区域，即关键区域。本发明进一步改变电路设计的布局以减少临界面积，从而降低在制造过程中发生故障的可能性。确定关键区域的方法包括通用运行，几何映射和Voronoi图。优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。

2. 发明申请

US20090100386A1 IC Layout Optimization to Improve Yield 有权
标题翻译： IC布局优化提高产量
公开(公告)号：US20090100386A1
公开(公告)日：2009-04-16
申请号：US12342353
申请日：2008-12-23
申请人： Robert J. Allen , Faye D. Baker , Albert M. Chu , Michael S. Gray , Jason Hibbeler , Daniel N. Maynard , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Faye D. Baker , Albert M. Chu , Michael S. Gray , Jason Hibbeler , Daniel N. Maynard , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Optimizing an integrated circuit design to improve manufacturing yield using manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The process further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.
摘要翻译：使用制造数据和算法优化集成电路设计以提高制造产量，以识别故障概率高的区域，即关键区域。该过程进一步改变电路设计的布局以减少临界面积，从而降低制造过程中发生故障的可能性。确定关键区域的方法包括通用运行，几何映射和Voronoi图。优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。

3. 发明授权

US07503020B2 IC layout optimization to improve yield 失效
标题翻译： IC布局优化提高产量
公开(公告)号：US07503020B2
公开(公告)日：2009-03-10
申请号：US11424922
申请日：2006-06-19
申请人： Robert J. Allen , Faye D. Baker , Albert M. Chu , Michael S. Gray , Jason Hibbeler , Daniel N. Maynard , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Faye D. Baker , Albert M. Chu , Michael S. Gray , Jason Hibbeler , Daniel N. Maynard , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.
摘要翻译：一种用于优化集成电路设计以提高制造产量的方法和服务。本发明使用制造数据和算法来识别故障概率高的区域，即关键区域。本发明进一步改变电路设计的布局以减少临界面积，从而降低在制造过程中发生故障的可能性。确定关键区域的方法包括通用运行，几何映射和Voronoi图。优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。

4. 发明申请

US20080168414A1 METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR DISPLAYING AND MODIFYING THE CRITICAL AREA OF AN INTEGRATED CIRCUIT DESIGN. 失效
标题翻译：用于显示和修改集成电路设计关键领域的方法，装置和计算机程序产品。
公开(公告)号：US20080168414A1
公开(公告)日：2008-07-10
申请号：US11620059
申请日：2007-01-05
申请人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.
摘要翻译：一种用于可视地指示有助于定义的关键区域图案的设计的一个或多个边缘之间的交互的方法，装置和计算机程序产品。

5. 发明授权

US07752589B2 Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design 失效
标题翻译：用于显示和修改集成电路设计的关键区域的方法，装置和计算机程序产品
公开(公告)号：US07752589B2
公开(公告)日：2010-07-06
申请号：US11620059
申请日：2007-01-05
申请人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.
摘要翻译：一种用于可视地指示有助于定义的关键区域图案的设计的一个或多个边缘之间的交互的方法，装置和计算机程序产品。

6. 发明授权

US07634745B2 Method for computing the critical area of compound fault mechanisms 失效
标题翻译：计算复合故障机制关键区域的方法
公开(公告)号：US07634745B2
公开(公告)日：2009-12-15
申请号：US11461805
申请日：2006-08-02
申请人： Robert J. Allen , Sarah C. Braasch , Mervyn Y. Tan
发明人： Robert J. Allen , Sarah C. Braasch , Mervyn Y. Tan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： In embodiments of a method critical area is calculated based on both independent and dependent compound fault mechanisms. Specifically, critical area is calculated by generating, for each simple fault mechanism in the compound fault mechanism, a map made up of polygonal regions, where values on a third dimensional z-axis represent the critical defect size for each single fault mechanism at a point x,y. These maps are overlaid and the planar faces (i.e., top surfaces) of each region of each map are projected onto the x,y plane in order to identify intersecting sub-regions. The dominant fault mechanism within each sub-region is identified based on an answer to predetermined Boolean expression and the critical areas for all of the sub-regions are accumulated in order to obtain the total critical area for the compound fault mechanism.
摘要翻译：在方法的实施例中，基于独立和依赖复合故障机制来计算关键区域。具体地说，关键区域是通过为复合故障机构中的每个简单故障机制产生由多边形区域组成的地图来计算的，其中第三维z轴上的值表示在一个点处的每个单个故障机构的临界缺陷尺寸 x，y。覆盖这些贴图，并且将每个贴图的每个区域的平面（即顶面）投影到x，y平面上，以便识别相交的子区域。基于对预定布尔表达式的答案来识别每个子区域内的主要故障机制，并且累积所有子区域的临界区域以获得复合故障机制的总临界面积。

7. 发明授权

US07302653B2 Probability of fault function determination using critical defect size map 失效
标题翻译：使用关键缺陷尺寸图故障函数确定的概率
公开(公告)号：US07302653B2
公开(公告)日：2007-11-27
申请号：US10906548
申请日：2005-02-24
申请人： Robert J. Allen , Mervyn Y. Tan
发明人： Robert J. Allen , Mervyn Y. Tan
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Methods, systems and program products for determining a probability of fault (POF) function using critical defect size maps. Methods for an exact or a sample POF function are provided. Critical area determinations can also be supplied based on the exact or sample POF functions. The invention provides a less computationally complex and storage-intensive methodology.
摘要翻译：使用关键缺陷尺寸图确定故障概率（POF）功能的方法，系统和程序产品。提供精确或样本POF功能的方法。也可以根据POF功能的准确或取样来提供关键区域测定。本发明提供了较少的计算复杂性和存储密集型方法。

8. 发明授权

US07310788B2 Sample probability of fault function determination using critical defect size map 失效
标题翻译：使用关键缺陷尺寸图的故障函数确定的样本概率
公开(公告)号：US07310788B2
公开(公告)日：2007-12-18
申请号：US10906549
申请日：2005-02-24
申请人： Robert J. Allen , Mervyn Y. Tan
发明人： Robert J. Allen , Mervyn Y. Tan
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/504
摘要： Methods, systems and program products for determining a probability of fault (POF) function using critical defect size maps. Methods for an exact or a sample POF function are provided. Critical area determinations can also be supplied based on the exact or sample POF functions. The invention provides a less computationally complex and storage-intensive methodology.
摘要翻译：使用关键缺陷尺寸图确定故障概率（POF）功能的方法，系统和程序产品。提供精确或样本POF功能的方法。也可以根据POF功能的准确或取样来提供关键区域测定。本发明提供了较少的计算复杂性和存储密集型方法。

9. 发明授权

US07240306B2 Integrated circuit layout critical area determination using Voronoi diagrams and shape biasing 有权
标题翻译：使用Voronoi图和形状偏置的集成电路布局临界区域确定
公开(公告)号：US07240306B2
公开(公告)日：2007-07-03
申请号：US10906553
申请日：2005-02-24
申请人： Robert J. Allen , Peter K. Chan , Evanthia Papadopoulou , Sarah C. Prue , Mervyn Y. Tan
发明人： Robert J. Allen , Peter K. Chan , Evanthia Papadopoulou , Sarah C. Prue , Mervyn Y. Tan
IPC分类号： G06F17/50 , G06F19/00 , G06F17/10 , G06F11/00 , G06K9/03 , G06K9/52
CPC分类号： G06F17/5081
摘要： Method, system and program product for determining a critical area in a region of an integrated circuit layout using Voronoi diagrams and shape biasing. The method includes the steps of generating a biased Voronoi diagram based on a layout geometry of the region and incorporating a shape bias; and determining the critical area for the region using the biased Voronoi diagram.
摘要翻译：用于使用Voronoi图和形状偏置来确定集成电路布局的区域中的临界区域的方法，系统和程序产品。该方法包括以下步骤：基于该区域的布局几何形状并结合形状偏差产生偏置Voronoi图; 并使用偏倚的Voronoi图确定该地区的关键区域。

10. 发明申请

US20080127004A1 METHOD FOR COMPUTING THE CRITICAL AREA OF COMPOUND FAULT MECHANISMS 失效
标题翻译：计算化合物故障机理关键领域的方法
公开(公告)号：US20080127004A1
公开(公告)日：2008-05-29
申请号：US11461805
申请日：2006-08-02
申请人： Robert J. Allen , Sarah C. Braasch , Mervyn Y. Tan
发明人： Robert J. Allen , Sarah C. Braasch , Mervyn Y. Tan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Disclosed is a method of calculating critical area based on both independent and dependent compound fault mechanisms. This critical area is calculated by generating, for each simple fault mechanism in the compound fault mechanism, a map made up of polygonal regions, where values on a third dimensional z-axis represent the critical defect size for each single fault mechanism at a point x,y. These maps are overlaid and the planar faces (i.e., top surfaces) of each region of each map are projected onto the x,y plane in order to identify intersecting sub-regions. The dominant fault mechanism within each sub-region is identified based on an answer to predetermined Boolean expression and the critical areas for all of the sub-regions are accumulated in order to obtain the total critical area for the compound fault mechanism.
摘要翻译：公开了一种基于独立和依赖复合故障机制来计算临界面积的方法。该关键区域通过为复合故障机制中的每个简单故障机制产生由多边形区域组成的地图来计算，其中第三维z轴上的值表示在点x处的每个单个故障机制的临界缺陷尺寸，y。覆盖这些贴图，并且将每个贴图的每个区域的平面（即，顶面）投影到x，y平面上，以便识别相交的子区域。基于对预定布尔表达式的答案来识别每个子区域内的主要故障机制，并且累积所有子区域的临界区域以获得复合故障机制的总临界面积。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式