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1. 发明授权

US6151693A Automated method of burn-in and endurance testing for embedded EEPROM 失效
标题翻译：嵌入式EEPROM的自动化老化和耐久性测试方法
公开(公告)号：US6151693A
公开(公告)日：2000-11-21
申请号：US99776
申请日：1998-06-19
申请人： Robert H. Arnold , Richard D. Bell , Ross A. Kohler , Richard J. McPartland , Paul K. Wheeler
发明人： Robert H. Arnold , Richard D. Bell , Ross A. Kohler , Richard J. McPartland , Paul K. Wheeler
IPC分类号： G11C29/08 , G11C29/00 , G11C7/00
CPC分类号： G11C29/08 , G11C16/04 , G11C2029/0401
摘要： An on-chip processor is used as a controller for burn-in and endurance testing of embedded non-volatile memory. An automated test machine downloads a test program into the non-volatile memory. The downloaded program contains a test program to be run on the non-volatile memory. When the burn-in or endurance test equipment activates the processor, the processor executes the program and performs a test on the non-volatile memory. The same method can be utilized to perform either the burn-in or endurance tests. Only the clock and reset lines are required to operate the test. Since the clock and reset lines are part of the processor's standard inputs, the method performs burn-in and endurance testing of an embedded non-volatile memory without bringing out the memory's address, data and control lines to the package pins of the integrated circuit. Since the clock and reset lines are part of the standard burn-in and endurance test equipment, the method also performs the testing without the use of expensive burn-in or endurance test equipment.
摘要翻译：片上处理器用作嵌入式非易失性存储器的老化和耐久性测试的控制器。自动测试机器将测试程序下载到非易失性存储器中。下载的程序包含要在非易失性存储器上运行的测试程序。当老化或耐久性测试设备激活处理器时，处理器执行程序并对非易失性存储器执行测试。可以使用相同的方法来执行老化或耐久性测试。只有时钟和复位线才能进行测试。由于时钟和复位线是处理器标准输入的一部分，因此该方法对嵌入式非易失性存储器进行老化和耐久性测试，而不会将存储器的地址，数据和控制线路输出到集成电路的封装引脚。由于时钟和复位线是标准老化和耐久性测试设备的一部分，所以该方法还可以在不使用昂贵的老化或耐久性测试设备的情况下进行测试。

2. 发明授权

US08516408B2 Optimization of circuits having repeatable circuit instances 失效
标题翻译：具有可重复电路实例的电路优化
公开(公告)号：US08516408B2
公开(公告)日：2013-08-20
申请号：US12471968
申请日：2009-05-26
申请人： Richard Bruce Dell , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Richard Bruce Dell , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L25/0657 , H01L25/18 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： Techniques for forming a first electronic circuit including a plurality of instances of a repeatable circuit element include the steps of: obtaining a total number of instances of the repeatable circuit element in a design of an IC including the first electronic circuit and at least a second electronic circuit; and configuring at least one functional parameter of the first electronic circuit as a function of the total number of instances of the repeatable circuit element in the IC to thereby satisfy a prescribed minimum composite manufacturing yield of the IC and/or at least one specification of the IC under prescribed operating conditions.
摘要翻译：用于形成包括可重复电路元件的多个实例的第一电子电路的技术包括以下步骤：在包括第一电子电路的IC的设计中获得可重复电路元件的实例的总数，以及至少第二电子电路以及将所述第一电子电路的至少一个功能参数配置为所述IC中的所述可重复电路元件的总数的函数，从而满足所述IC的规定的最小复合制造收益率和/或所述IC的至少一个规格 IC在规定的运行条件下。

3. 发明授权

US07930615B2 Memory device with error correction capability and preemptive partial word write operation 有权
标题翻译：具有纠错能力和抢先部分字写操作的存储器件
公开(公告)号：US07930615B2
公开(公告)日：2011-04-19
申请号：US11756011
申请日：2007-05-31
申请人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1044 , G11C2029/0411
摘要： A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform a partial word write operation in which an error correction code encode process for the given retrieved word is initiated prior to completion of an error correction code decode process for the given retrieved word based on an assumption that the error correction code decode process will not indicate an error in the given retrieved word. If the error correction code decode process when completed indicates an error in the given retrieved word, the error in the given retrieved word is corrected in the error correction circuitry, and the error correction code encode process is restarted using the corrected word. The error correction code decode process and an associated correct process are thereby removed from a critical timing path of the partial word write operation.
摘要翻译：存储器件包括耦合到存储器阵列的存储器阵列和纠错电路。存储器装置被配置为执行部分字写入操作，其中在完成针对给定检索字的纠错码解码处理之前，针对给定检索到的字的纠错码编码处理是基于错误校正代码解码过程不会在给定的检索词中指示错误。如果完成时的纠错码解码处理指示给定检索字中的错误，则在纠错电路中校正给定检索字中的错误，并使用校正字重新开始纠错码编码处理。因此，从部分字写入操作的临界定时路径移除纠错码解码处理和相关联的正确处理。

4. 发明申请

US20110055660A1 High-Reliability Memory 有权
标题翻译：高可靠性内存
公开(公告)号：US20110055660A1
公开(公告)日：2011-03-03
申请号：US12550978
申请日：2009-08-31
申请人： Dennis E. Dudeck , Ross A. Kohler , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner
发明人： Dennis E. Dudeck , Ross A. Kohler , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1048 , G11C29/42 , G11C29/76 , H03M13/09 , H03M13/19
摘要： A memory circuit includes a memory including a plurality of primary memory elements, and an error correction circuit coupled to the memory and operative to detect an error in at least one of the primary memory elements and to provide corrected data corresponding to the primary memory element. The memory circuit further includes at least one spare memory element and a control circuit operative to replace at least one of the primary memory elements with the spare memory element as a function of results generated by the error correction circuit.
摘要翻译：存储器电路包括存储器，其包括多个主存储器元件，以及错误校正电路，其耦合到存储器并且可操作以检测至少一个主存储器元件中的错误，并提供对应于主存储器元件的校正数据。存储器电路还包括至少一个备用存储器元件和控制电路，其可操作以根据由纠错电路产生的结果将备用存储器元件替换为主存储元件中的至少一个。

5. 发明申请

US20100271064A1 Integrated Circuit Self-Monitored Burn-In 失效
标题翻译：集成电路自我监控老化
公开(公告)号：US20100271064A1
公开(公告)日：2010-10-28
申请号：US12431053
申请日：2009-04-28
申请人： Ross A. Kohler , Richard J. McPartland , Larry Christopher Wall , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Larry Christopher Wall , Wayne E. Werner
IPC分类号： G01R31/02
CPC分类号： G01R31/2856 , G01R31/3187 , G01R31/31935 , G11C29/12 , G11C29/4401 , G11C29/50
摘要： An IC adapted for self-monitored burn-in includes a first memory and at least one BIST circuit coupled to the memory and operative to test the IC by executing a burn-in test and to generate test results indicative of at least one parameter of the burn-in test. The test results are at least temporarily stored in the first memory as a function of a first control signal.
摘要翻译：适于自我监测老化的IC包括第一存储器和耦合到存储器的至少一个BIST电路，并且可操作以通过执行老化测试来测试IC，并产生指示至少一个参数的测试结果老化测试测试结果至少临时存储在第一存储器中作为第一控制信号的函数。

6. 发明授权

US08566377B2 Secure random number generator 有权
标题翻译：安全随机数发生器
公开(公告)号：US08566377B2
公开(公告)日：2013-10-22
申请号：US12934510
申请日：2008-05-23
申请人： Edward B. Harris , Richard Hogg , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Edward B. Harris , Richard Hogg , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , G06F11/1008 , G11C11/412 , G11C2029/0411
摘要： A random number generator circuit includes a first memory having multiple storage elements. Each of the storage elements has an initial state corresponding thereto when powered up by a voltage supply source applied to the first memory. The first memory is operative to generate a first signal including multiple bits indicative of the respective initial states of the storage elements. The random number generator circuit further includes an error correction circuit coupled to the first memory. The error correction circuit is operative to receive the first signal and to correct at least one bit in the first signal that is not repeatable upon successive applications of power to the first memory to thereby generate a second signal. The second signal is a random number that is repeatable upon successive applications of power to the first memory.
摘要翻译：随机数发生器电路包括具有多个存储元件的第一存储器。当由施加到第一存储器的电压源供电时，每个存储元件具有与之对应的初始状态。第一存储器用于产生包括指示存储元件的相应初始状态的多个位的第一信号。随机数发生器电路还包括耦合到第一存储器的纠错电路。误差校正电路可操作以接收第一信号并且校正第一信号中的至少一个位，其在连续施加电力到第一存储器从而产生第二信号时不重复。第二信号是在连续向第一存储器施加电力时可重复的随机数。

7. 发明授权

US08023348B2 Method and apparatus for testing a memory device 有权
标题翻译：用于测试存储器件的方法和装置
公开(公告)号：US08023348B2
公开(公告)日：2011-09-20
申请号：US12443776
申请日：2007-10-29
申请人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G11C29/00
CPC分类号： G11C8/08 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50016 , G11C2029/1202
摘要： Techniques for testing a semiconductor memory device are provided. The memory device includes a plurality of memory cells and a plurality of row lines and column lines connected to the memory cells for selectively accessing one or more of the memory cells. The method includes the steps of: applying a first voltage to at least a given one of the row lines corresponding to at least a given one of the memory cells to be tested, the first voltage being selected to stress at least one performance characteristic of the memory device, the first voltage being different than a second voltage applied to the given one of the row lines for accessing at least one of the memory cells during normal operation of the memory device; exercising the memory device in accordance with prescribed testing parameters; and identifying whether the memory device is operable within prescribed margins of the testing parameters.
摘要翻译：提供了用于测试半导体存储器件的技术。存储器件包括多个存储器单元和连接到存储器单元的多个行线和列线，用于选择性地访问一个或多个存储器单元。该方法包括以下步骤：将至少一个对应于待测试的存储器单元中的给定一个行的行中的至少一个施加第一电压，选择第一电压以强调第一电压的至少一个性能特征存储器件，所述第一电压不同于施加到所述给定行之一行的第二电压，用于在所述存储器件的正常操作期间访问所述存储器单元中的至少一个; 根据规定的测试参数锻炼记忆装置; 以及识别存储器件是否在测试参数的规定余量内可操作。

8. 发明申请

US20100131825A1 Memory Device with Error Correction Capability and Efficient Partial Word Write Operation 有权
标题翻译：具有纠错能力和高效部分字写入操作的存储器件
公开(公告)号：US20100131825A1
公开(公告)日：2010-05-27
申请号：US11994740
申请日：2007-04-26
申请人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： H03M13/05 , G06F12/00 , G06F11/10
CPC分类号： G11C29/52 , G06F11/1008
摘要： A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform at least a partial word write operation and a read operation, with the partial word write operation comprising a read phase and a write phase. The write phase of the partial word write operation occurs in the same clock cycle of the memory device as the read operation by, for example, time multiplexing bitlines of the memory array within the clock cycle between the write phase of the partial word write operation and the read operation. Thus, the partial word write operation appears to a higher-level system incorporating or otherwise utilizing the memory device as if that operation requires only a single clock cycle of the memory device.
摘要翻译：存储器件包括耦合到存储器阵列的存储器阵列和纠错电路。存储器件被配置为执行至少部分字写入操作和读取操作，其中部分字写入操作包括读取阶段和写入阶段。部分字写入操作的写入阶段在存储器件的相同时钟周期中发生在与读取操作相同的时钟周期中，例如在部分字写入操作的写入相位与时钟周期内的存储器阵列的时间复用位线之间，读操作。因此，部分字写入操作对于包含或以其他方式利用存储器件的更高级系统出现，就好像该操作仅需要存储器件的单个时钟周期。

9. 发明申请

US20090196098A1 Multiple-Level Memory with Analog Read 有权
标题翻译：具有模拟读取功能的多级存储器
公开(公告)号：US20090196098A1
公开(公告)日：2009-08-06
申请号：US12023092
申请日：2008-01-31
申请人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G11C16/04 , G11C16/06 , G11C7/00
CPC分类号： G11C27/005 , G11C7/06 , G11C11/5642 , G11C29/00
摘要： A memory circuit includes a plurality of memory cells, each of the memory cells being operative to store multiple bits of data therein, and a plurality of column lines and row lines coupled to the memory cells for selectively accessing the memory cells. The circuit further includes multiple sense amplifiers, each of the sense amplifiers being connected to a corresponding one of the column lines and being operative to detect an electric charge stored in a selected one of the memory cells coupled to the corresponding column line and to generate an analog signal indicative of the stored electric charge. An analog multiplexer is connected to the sense amplifiers. The analog multiplexer is operative to receive the respective analog signals from the sense amplifiers and to generate an analog output signal having a magnitude which varies in time as a function of the respective analog signals from the sense amplifiers.
摘要翻译：存储器电路包括多个存储器单元，每个存储单元可操作以在其中存储多个数据位，并且多个列线和行线耦合到存储器单元以选择性地访问存储器单元。该电路还包括多个读出放大器，每个读出放大器连接到相应的列线之一，并且可操作以检测存储在耦合到对应的列线的存储器单元中选定的一个中的电荷，并产生指示所存储的电荷的模拟信号。模拟多路复用器连接到读出放大器。模拟多路复用器可操作以从读出放大器接收相应的模拟信号，并产生具有随时间变化的幅度的模拟输出信号，作为来自读出放大器的相应模拟信号的函数。

10. 发明申请

US20090141575A1 Method and Apparatus for Idle Cycle Refresh Request in Dram 有权
标题翻译：用于空闲周期刷新请求的方法和装置
公开(公告)号：US20090141575A1
公开(公告)日：2009-06-04
申请号：US11948214
申请日：2007-11-30
申请人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C2211/4061 , G11C2211/4065
摘要： Generally, methods and apparatus are provided for idle cycle refresh request in a dynamic random access memory. According to one aspect of the invention, a dynamic random access memory is refreshed by determining if a refresh of the dynamic random access memory is required; and allocating an idle cycle sequence to refresh at least a portion of the dynamic random access memory only if the determining step determines that a refresh of the dynamic random access memory is required. A refresh flag can optionally be set if a refresh is required. The idle cycle sequence comprises one or more idle cycles. The idle cycle sequence can optionally be allocated within a predefined duration of the refresh flag being set. The step of determining step whether a refresh of the dynamic random access memory is required can be based on real-time or expected conditions.
摘要翻译：通常，为动态随机存取存储器中的空闲周期刷新请求提供方法和装置。根据本发明的一个方面，通过确定是否需要刷新动态随机存取存储器来刷新动态随机存取存储器; 以及仅当确定步骤确定需要动态随机存取存储器的刷新时，才分配空闲周期序列来刷新动态随机存取存储器的至少一部分。如果需要刷新，可以选择设置刷新标志。空闲周期序列包括一个或多个空闲周期。空闲周期序列可以可选地在被设置的刷新标志的预定持续时间内被分配。确定步骤是否需要刷新动态随机存取存储器的步骤可以基于实时或预期的条件。

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