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1. 发明授权

US08516408B2 Optimization of circuits having repeatable circuit instances 失效
标题翻译：具有可重复电路实例的电路优化
公开(公告)号：US08516408B2
公开(公告)日：2013-08-20
申请号：US12471968
申请日：2009-05-26
申请人： Richard Bruce Dell , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Richard Bruce Dell , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L25/0657 , H01L25/18 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： Techniques for forming a first electronic circuit including a plurality of instances of a repeatable circuit element include the steps of: obtaining a total number of instances of the repeatable circuit element in a design of an IC including the first electronic circuit and at least a second electronic circuit; and configuring at least one functional parameter of the first electronic circuit as a function of the total number of instances of the repeatable circuit element in the IC to thereby satisfy a prescribed minimum composite manufacturing yield of the IC and/or at least one specification of the IC under prescribed operating conditions.
摘要翻译：用于形成包括可重复电路元件的多个实例的第一电子电路的技术包括以下步骤：在包括第一电子电路的IC的设计中获得可重复电路元件的实例的总数，以及至少第二电子电路以及将所述第一电子电路的至少一个功能参数配置为所述IC中的所述可重复电路元件的总数的函数，从而满足所述IC的规定的最小复合制造收益率和/或所述IC的至少一个规格 IC在规定的运行条件下。

2. 发明授权

US07872929B2 Accessing memory cells in a memory circuit 有权
标题翻译：访问存储器电路中的存储单元
公开(公告)号：US07872929B2
公开(公告)日：2011-01-18
申请号：US12431280
申请日：2009-04-28
申请人： Richard Bruce Dell , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Richard Bruce Dell , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G11C29/00
CPC分类号： G11C8/10 , G11C5/06 , G11C7/22 , G11C7/24 , G11C11/4076 , G11C11/4078 , G11C29/028 , G11C29/50 , G11C29/70 , G11C29/88 , G11C2029/1208 , G11C2029/5002 , H01L25/0657 , H01L25/18 , H01L2224/16145 , H01L2225/06568 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： Techniques for accessing a memory cell in a memory circuit include: receiving a request to access a selected memory cell in the memory circuit; determining whether the selected memory cell corresponds to a normal memory cell or a weak memory cell in the memory circuit; accessing the selected memory cell using a first set of control parameters when the selected memory cell corresponds to a normal memory cell, wherein the selected memory cell provides correct data under prescribed operating specifications when accessed using the first set of control parameters; and accessing the selected memory cell using a second set of control parameters when the selected memory cell corresponds to a weak memory cell, wherein the selected memory cell provides correct data under the prescribed operating specifications when accessed using the second set of control parameters and provides incorrect data under the prescribed operating specifications when accessed using the first set of control parameters.
摘要翻译：用于访问存储器电路中的存储器单元的技术包括：接收访问存储器电路中的选定存储单元的请求; 确定所选择的存储器单元是否对应于存储器电路中的正常存储器单元或弱存储器单元; 当所选择的存储器单元对应于正常存储器单元时，使用第一组控制参数访问所选择的存储器单元，其中当使用第一组控制参数访问时，所选择的存储器单元在规定的操作规范下提供正确的数据; 以及当所选择的存储器单元对应于弱存储器单元时，使用第二组控制参数访问所选择的存储器单元，其中当使用第二组控制参数访问时，所选存储单元在规定的操作规范下提供正确的数据，并且提供不正确的使用第一组控制参数访问时，在规定的操作规范下的数据。

3. 发明申请

US20100301926A1 Optimization of Circuits Having Repeatable Circuit Instances 失效
标题翻译：具有可重复电路实例的电路优化
公开(公告)号：US20100301926A1
公开(公告)日：2010-12-02
申请号：US12471968
申请日：2009-05-26
申请人： Richard Bruce Dell , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Richard Bruce Dell , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G05F1/10 , G06F17/50 , H01L25/00
CPC分类号： G06F17/5068 , H01L25/0657 , H01L25/18 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： Techniques for forming a first electronic circuit including a plurality of instances of a repeatable circuit element include the steps of: obtaining a total number of instances of the repeatable circuit element in a design of an IC including the first electronic circuit and at least a second electronic circuit; and configuring at least one functional parameter of the first electronic circuit as a function of the total number of instances of the repeatable circuit element in the IC to thereby satisfy a prescribed minimum composite manufacturing yield of the IC and/or at least one specification of the IC under prescribed operating conditions.
摘要翻译：用于形成包括可重复电路元件的多个实例的第一电子电路的技术包括以下步骤：在包括第一电子电路的IC的设计中获得可重复电路元件的实例的总数，以及至少第二电子电路以及将所述第一电子电路的至少一个功能参数配置为所述IC中的所述可重复电路元件的总数的函数，从而满足所述IC的规定的最小复合制造收益率和/或所述IC的至少一个规格 IC在规定的运行条件下。

4. 发明授权

US07940594B2 Method and apparatus for increasing yield in a memory device 有权
标题翻译：用于增加存储器件中的产量的方法和装置
公开(公告)号：US07940594B2
公开(公告)日：2011-05-10
申请号：US12295518
申请日：2008-01-30
申请人： Richard Bruce Dell , Ross A. Kohler , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner
发明人： Richard Bruce Dell , Ross A. Kohler , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner
IPC分类号： G11C5/14
CPC分类号： G11C16/30 , G11C5/063 , G11C5/147 , Y10T307/352
摘要： An electronic circuit includes multiple circuit elements arranged into multiple distinct subdivisions, each subdivision having a separate voltage supply connection for conveying power to the subdivision. The electronic circuit further includes a controller including multiple outputs, each of the outputs being connected to a corresponding one of the voltage supply connections. When a given one of the subdivisions does not include a weak circuit element, the controller supplies a first voltage level to the given subdivision via the corresponding voltage supply connection. When the given subdivision includes at least one weak circuit element, the controller is operative to supply at least a second voltage level to the given subdivision via the corresponding voltage supply connection, the second voltage level being greater than the first voltage level.
摘要翻译：电子电路包括布置成多个不同子部分的多个电路元件，每个细分具有用于将功率输送到细分的单独的电压供应连接。电子电路还包括具有多个输出的控制器，每个输出端连接到对应的一个电压供应连接。当给定的一个子部分不包括弱电路元件时，控制器通过相应的电压供应连接器向给定的分区提供第一电压电平。当给定细分包括至少一个弱电路元件时，控制器可操作以经由对应的电压供应连接向给定细分提供至少第二电压电平，第二电压电平大于第一电压电平。

5. 发明申请

US20100271891A1 Accessing Memory Cells in a Memory Circuit 有权
标题翻译：访问存储器电路中的存储单元
公开(公告)号：US20100271891A1
公开(公告)日：2010-10-28
申请号：US12431280
申请日：2009-04-28
申请人： Richard Bruce Dell , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Richard Bruce Dell , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G11C29/00 , G11C8/00 , G11C7/00 , G06F11/00 , G06F11/27
CPC分类号： G11C8/10 , G11C5/06 , G11C7/22 , G11C7/24 , G11C11/4076 , G11C11/4078 , G11C29/028 , G11C29/50 , G11C29/70 , G11C29/88 , G11C2029/1208 , G11C2029/5002 , H01L25/0657 , H01L25/18 , H01L2224/16145 , H01L2225/06568 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： Techniques for accessing a memory cell in a memory circuit include: receiving a request to access a selected memory cell in the memory circuit; determining whether the selected memory cell corresponds to a normal memory cell or a weak memory cell in the memory circuit; accessing the selected memory cell using a first set of control parameters when the selected memory cell corresponds to a normal memory cell, wherein the selected memory cell provides correct data under prescribed operating specifications when accessed using the first set of control parameters; and accessing the selected memory cell using a second set of control parameters when the selected memory cell corresponds to a weak memory cell, wherein the selected memory cell provides correct data under the prescribed operating specifications when accessed using the second set of control parameters and provides incorrect data under the prescribed operating specifications when accessed using the first set of control parameters.
摘要翻译：用于访问存储器电路中的存储器单元的技术包括：接收访问存储器电路中的选定存储单元的请求; 确定所选择的存储器单元是否对应于存储器电路中的正常存储器单元或弱存储器单元; 当所选择的存储器单元对应于正常存储器单元时，使用第一组控制参数访问所选择的存储器单元，其中当使用第一组控制参数访问时，所选择的存储器单元在规定的操作规范下提供正确的数据; 以及当所选择的存储器单元对应于弱存储器单元时，使用第二组控制参数访问所选择的存储器单元，其中当使用第二组控制参数访问时，所选存储单元在规定的操作规范下提供正确的数据，并且提供不正确的使用第一组控制参数访问时，在规定的操作规范下的数据。

6. 发明申请

US20100238751A1 Method and Apparatus for Increasing Yield in a Memory Device 有权
标题翻译：用于增加存储器件中的产量的方法和装置
公开(公告)号：US20100238751A1
公开(公告)日：2010-09-23
申请号：US12295518
申请日：2008-01-30
申请人： Richard Bruce Dell , Ross A. Kohler , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner
发明人： Richard Bruce Dell , Ross A. Kohler , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner
IPC分类号： G11C5/14 , H02J4/00
CPC分类号： G11C16/30 , G11C5/063 , G11C5/147 , Y10T307/352
摘要： An electronic circuit includes multiple circuit elements arranged into multiple distinct subdivisions, each subdivision having a separate voltage supply connection for conveying power to the subdivision. The electronic circuit further includes a controller including multiple outputs, each of the outputs being connected to a corresponding one of the voltage supply connections. When a given one of the subdivisions does not include a weak circuit element, the controller supplies a first voltage level to the given subdivision via the corresponding voltage supply connection. When the given subdivision includes at least one weak circuit element, the controller is operative to supply at least a second voltage level to the given subdivision via the corresponding voltage supply connection, the second voltage level being greater than the first voltage level.
摘要翻译：电子电路包括布置成多个不同子部分的多个电路元件，每个细分具有用于将功率输送到细分的单独的电压供应连接。电子电路还包括具有多个输出的控制器，每个输出端连接到对应的一个电压供应连接。当给定的一个子部分不包括弱电路元件时，控制器通过相应的电压供应连接器向给定的分区提供第一电压电平。当给定细分包括至少一个弱电路元件时，控制器可操作以经由对应的电压供应连接向给定细分提供至少第二电压电平，第二电压电平大于第一电压电平。

7. 发明授权

US07930615B2 Memory device with error correction capability and preemptive partial word write operation 有权
标题翻译：具有纠错能力和抢先部分字写操作的存储器件
公开(公告)号：US07930615B2
公开(公告)日：2011-04-19
申请号：US11756011
申请日：2007-05-31
申请人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1044 , G11C2029/0411
摘要： A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform a partial word write operation in which an error correction code encode process for the given retrieved word is initiated prior to completion of an error correction code decode process for the given retrieved word based on an assumption that the error correction code decode process will not indicate an error in the given retrieved word. If the error correction code decode process when completed indicates an error in the given retrieved word, the error in the given retrieved word is corrected in the error correction circuitry, and the error correction code encode process is restarted using the corrected word. The error correction code decode process and an associated correct process are thereby removed from a critical timing path of the partial word write operation.
摘要翻译：存储器件包括耦合到存储器阵列的存储器阵列和纠错电路。存储器装置被配置为执行部分字写入操作，其中在完成针对给定检索字的纠错码解码处理之前，针对给定检索到的字的纠错码编码处理是基于错误校正代码解码过程不会在给定的检索词中指示错误。如果完成时的纠错码解码处理指示给定检索字中的错误，则在纠错电路中校正给定检索字中的错误，并使用校正字重新开始纠错码编码处理。因此，从部分字写入操作的临界定时路径移除纠错码解码处理和相关联的正确处理。

8. 发明申请

US20110055660A1 High-Reliability Memory 有权
标题翻译：高可靠性内存
公开(公告)号：US20110055660A1
公开(公告)日：2011-03-03
申请号：US12550978
申请日：2009-08-31
申请人： Dennis E. Dudeck , Ross A. Kohler , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner
发明人： Dennis E. Dudeck , Ross A. Kohler , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1048 , G11C29/42 , G11C29/76 , H03M13/09 , H03M13/19
摘要： A memory circuit includes a memory including a plurality of primary memory elements, and an error correction circuit coupled to the memory and operative to detect an error in at least one of the primary memory elements and to provide corrected data corresponding to the primary memory element. The memory circuit further includes at least one spare memory element and a control circuit operative to replace at least one of the primary memory elements with the spare memory element as a function of results generated by the error correction circuit.
摘要翻译：存储器电路包括存储器，其包括多个主存储器元件，以及错误校正电路，其耦合到存储器并且可操作以检测至少一个主存储器元件中的错误，并提供对应于主存储器元件的校正数据。存储器电路还包括至少一个备用存储器元件和控制电路，其可操作以根据由纠错电路产生的结果将备用存储器元件替换为主存储元件中的至少一个。

9. 发明申请

US20100271064A1 Integrated Circuit Self-Monitored Burn-In 失效
标题翻译：集成电路自我监控老化
公开(公告)号：US20100271064A1
公开(公告)日：2010-10-28
申请号：US12431053
申请日：2009-04-28
申请人： Ross A. Kohler , Richard J. McPartland , Larry Christopher Wall , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Larry Christopher Wall , Wayne E. Werner
IPC分类号： G01R31/02
CPC分类号： G01R31/2856 , G01R31/3187 , G01R31/31935 , G11C29/12 , G11C29/4401 , G11C29/50
摘要： An IC adapted for self-monitored burn-in includes a first memory and at least one BIST circuit coupled to the memory and operative to test the IC by executing a burn-in test and to generate test results indicative of at least one parameter of the burn-in test. The test results are at least temporarily stored in the first memory as a function of a first control signal.
摘要翻译：适于自我监测老化的IC包括第一存储器和耦合到存储器的至少一个BIST电路，并且可操作以通过执行老化测试来测试IC，并产生指示至少一个参数的测试结果老化测试测试结果至少临时存储在第一存储器中作为第一控制信号的函数。

10. 发明授权

US08566377B2 Secure random number generator 有权
标题翻译：安全随机数发生器
公开(公告)号：US08566377B2
公开(公告)日：2013-10-22
申请号：US12934510
申请日：2008-05-23
申请人： Edward B. Harris , Richard Hogg , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Edward B. Harris , Richard Hogg , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , G06F11/1008 , G11C11/412 , G11C2029/0411
摘要： A random number generator circuit includes a first memory having multiple storage elements. Each of the storage elements has an initial state corresponding thereto when powered up by a voltage supply source applied to the first memory. The first memory is operative to generate a first signal including multiple bits indicative of the respective initial states of the storage elements. The random number generator circuit further includes an error correction circuit coupled to the first memory. The error correction circuit is operative to receive the first signal and to correct at least one bit in the first signal that is not repeatable upon successive applications of power to the first memory to thereby generate a second signal. The second signal is a random number that is repeatable upon successive applications of power to the first memory.
摘要翻译：随机数发生器电路包括具有多个存储元件的第一存储器。当由施加到第一存储器的电压源供电时，每个存储元件具有与之对应的初始状态。第一存储器用于产生包括指示存储元件的相应初始状态的多个位的第一信号。随机数发生器电路还包括耦合到第一存储器的纠错电路。误差校正电路可操作以接收第一信号并且校正第一信号中的至少一个位，其在连续施加电力到第一存储器从而产生第二信号时不重复。第二信号是在连续向第一存储器施加电力时可重复的随机数。

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