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1. 发明授权

US4617479A Programmable logic array device using EPROM technology 失效
标题翻译：可编程逻辑阵列器件采用EPROM技术
公开(公告)号：US4617479A
公开(公告)日：1986-10-14
申请号：US607018
申请日：1984-05-03
申请人： Robert F. Hartmann , Sau-Ching Wong , Yiu-Fai Chan , Jung-Hsing Ou
发明人： Robert F. Hartmann , Sau-Ching Wong , Yiu-Fai Chan , Jung-Hsing Ou
IPC分类号： H03K5/02 , H03K19/094 , H03K19/177 , G06F7/00 , H03K19/20
CPC分类号： H03K19/17712 , H03K19/09425 , H03K5/023
摘要： The programmable logic array device basically comprises a programmable AND array (FIGS. 5, 11) having a plurality of memory cells (30, 31) arranged in addressable rows (40-45) and columns (32-38) and which can be individually programmed to contain logic data; an input circuit (FIG. 9) for receiving an input signal and for developing a buffered signal corresponding thereto; a first row driver (FIG. 10) responsive to the buffered signal and operative to interrogate a particular row of the memory cells and to cause the AND array to output signals corresponding to the data contained therein; first sensing circuitry (FIG. 12) for sensing the signals output by the AND array and for developing corresponding data signals which are the logical OR of signals output by the AND array; first output terminal circuitry; and first switching circuitry (FIG. 14) responsive to a control signal and operative to couple the data signal either into the storage circuitry or to the output terminal circuitry (FIG. 16). The device has the advantages generally of greater logic density and lower system power than standard family logic components.
摘要翻译：可编程逻辑阵列器件基本上包括一个可编程AND阵列（图5,11），其具有布置在可寻址行（40-45）和列（32-38）中的多个存储单元（30,31），并且可以单独地编程为包含逻辑数据; 输入电路（图9），用于接收输入信号并用于开发与其对应的缓冲信号; 第一行驱动器（图10），响应于所缓冲的信号并且可操作以询问存储器单元的特定行并使AND阵列输出与其中包含的数据相对应的信号; 第一感测电路（图12），用于感测由AND阵列输出的信号，并用于开发对应的数据信号，该数据信号是由AND阵列输出的信号的逻辑或; 第一输出端子电路; 和第一切换电路（图14），其响应于控制信号并且可操作以将数据信号耦合到存储电路或输出终端电路（图16）。该装置通常具有比标准系列逻辑组件更大的逻辑密度和更低的系统功率的优点。

2. 发明授权

US4713792A Programmable macrocell using eprom or eeprom transistors for architecture control in programmable logic circuits 失效
标题翻译：可编程宏单元使用eprom或eeprom晶体管进行可编程逻辑电路中的架构控制
公开(公告)号：US4713792A
公开(公告)日：1987-12-15
申请号：US742089
申请日：1985-06-06
申请人： Robert F. Hartmann , Yiu-Fai Chan , Robert J. Frankovich , Jung-Hsing Ou , Hock C. So , Sau-Ching Wong
发明人： Robert F. Hartmann , Yiu-Fai Chan , Robert J. Frankovich , Jung-Hsing Ou , Hock C. So , Sau-Ching Wong
IPC分类号： G11C17/00 , G11C16/04 , H01L21/82 , H01L21/8247 , H01L29/788 , H01L29/792 , H03K17/693 , H03K19/173 , H03K19/177 , G06F1/00
CPC分类号： H03K19/1736 , H03K17/693 , H03K19/1737
摘要： A programmable macrocell 28 for use in an integrated circuit device including an electronic circuit 32 responsive to control signals and operative to perform particular operations selected by the control signals on input data signals and to develop commensurate output signals, and one or more architecture control circuits 30 each including a programmable EPROM device 34 which when programmed generates a logic signal of a first state and when unprogrammed generates a logic signal of a second state, a read and write control circuit 36 responsive to input program data signals and a corresponding address signal and operative to program the EPROM device 34 by applying a programming potential thereto, and a sensing circuit 38 for sensing the programmed or unprogrammed status of the EPROM device 34 and for developing a commensurate control signal for input to the electronic circuit 32.
摘要翻译：一种用于集成电路设备的可编程宏单元28，其包括响应于控制信号的电子电路32，并且可操作以执行由输入数据信号上的控制信号选择的特定操作并且开发相应的输出信号，以及一个或多个架构控制电路30 每个都包括一个可编程EPROM器件34，当被编程时产生第一状态的逻辑信号，并且当未编程产生第二状态的逻辑信号时，读和写控制电路36响应输入的程序数据信号和对应的地址信号，通过向其施加编程电位来对EPROM器件34进行编程;以及感测电路38，用于感测EPROM器件34的编程状态或未编程状态，并用于形成相应的控制信号以输入到电子电路32。

3. 发明授权

US4774421A Programmable logic array device using EPROM technology 失效
标题翻译：可编程逻辑阵列器件采用EPROM技术
公开(公告)号：US4774421A
公开(公告)日：1988-09-27
申请号：US907075
申请日：1986-09-12
申请人： Robert F. Hartmann , Sau-Ching Wong , Yiu-Fai Chan , Jung-Hsing Ou
发明人： Robert F. Hartmann , Sau-Ching Wong , Yiu-Fai Chan , Jung-Hsing Ou
IPC分类号： H03K5/02 , H03K17/693 , H03K19/094 , H03K19/173 , H03K19/177
CPC分类号： H03K17/693 , H03K19/09425 , H03K19/1736 , H03K19/1737 , H03K19/17712 , H03K5/023
摘要： A programmable logic array device basically comprising a programmable AND gate array (FIGS. 5, 11) having addressable rows (40-45) and columns (32-38) or memory cells (30, 31) which can be individually programmed to represent logic data; an input signal receiving circuit (FIG. 9) for developing a corresponding buffered input signal; a first row driver (FIG. 10) responsive to the buffered signal and operative to cause a particular row of memory cells in an AND array (FIG. 11) to output corresponding logical product of AND-input signals, OR/NOR sensing circuitry (FIG. 12) for sensing the AND array product signals and for developing therefrom corresponding logical OR sum signals; circuit means output terminal circuitry; output switching circuitry (FIG. 14) responsive to a control signal and operative to couple either the circuit means output signal or a registered (FIG. 13) output to a device input or output terminal (FIG. 16); feedback switching circuitry similarly responsive to a control signal and operative to couple either the circuit means output signal, registered output signal, or feedback signal to a row driver; and Reprogrammable Architecture control circuitry (FIG. 24) to provide control signals to said switching circuitry. The device has the advantages of increased density of useable logic functions, and decreased power consumption.
摘要翻译：可编程逻辑阵列器件基本上包括具有可寻址行（40-45）和列（32-38）或存储器单元（30,31）的可编程与门阵列（图5,11），其可以被单独编程以表示逻辑数据; 输入信号接收电路（图9），用于开发相应的缓冲输入信号; 第一行驱动器（图10），响应于缓冲的信号并且可操作以使AND阵列（图11）中的特定行的存储器单元输出对应的AND输入信号的逻辑积OR / NOR感测电路（图12），用于感测AND阵列产品信号并用于从其产生相应的逻辑或和信号; 电路表示输出端子电路; 输出切换电路（图14），响应于控制信号并且可操作地将电路装置输出信号或注册的（图13）输出耦合到设备输入或输出端子（图16）; 反馈切换电路类似地响应于控制信号并且可操作地将电路装置的输出信号，已注册的输出信号或反馈信号耦合到行驱动器; 和可重编程架构控制电路（图24），以向所述开关电路提供控制信号。该器件具有可用逻辑功能密度增加，功耗降低的优点。

4. 发明授权

US4899070A Bit line sense amplifier for programmable logic devices 失效
标题翻译：用于可编程逻辑器件的位线读出放大器
公开(公告)号：US4899070A
公开(公告)日：1990-02-06
申请号：US218556
申请日：1988-07-13
申请人： Jung-Hsing Ou , Sau-Ching Wong
发明人： Jung-Hsing Ou , Sau-Ching Wong
IPC分类号： G11C16/26
CPC分类号： G11C16/26
摘要： In a programmable logic device, switching speed is improved by preventing the bit line potential from going excessively close to ground even when large numbers of word line connections to the ground conductor are made. In addition, bit line pull up to logic 1 is effected more rapidly (without retarding bit line pull down to logic 0) by having two transistors connected in parallel with one another between the reference potential source and the bit line. One of these transistors is on all the time providing a relatively small leakage current. The other transistor is on only while the bit line is at logic 0, thereby speeding pull up to logic 1 and then shutting off so as not to impede subsequent return to logic 0.
摘要翻译：在可编程逻辑器件中，即使当进行大量与接地导体的字线连接时，也可以通过防止位线电位过分靠近接地而提高开关速度。此外，通过使两个晶体管在参考电位源和位线之间彼此并联连接，上升到逻辑1的位线更快地实现（不将位线下拉到逻辑0）。这些晶体管中的一个始终提供相对较小的漏电流。另一个晶体管只在位线处于逻辑0时导通，从而加速上拉至逻辑1，然后关断，以免后续返回到逻辑0。

5. 发明授权

US4912342A Programmable logic device with array blocks with programmable clocking 失效
标题翻译：具有可编程时钟的阵列模块的可编程逻辑器件
公开(公告)号：US4912342A
公开(公告)日：1990-03-27
申请号：US407411
申请日：1989-09-14
申请人： Sau-Ching Wong , Hock-Chuen So , Stanley J. Kopec, Jr. , Robert F. Hartmann
发明人： Sau-Ching Wong , Hock-Chuen So , Stanley J. Kopec, Jr. , Robert F. Hartmann
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/1774 , H01L2224/05554 , H01L2224/49113
摘要： A programmable logic device having a relatively small number of programmable product terms ("P-terms") feeding each fixed combinatorial logic device, and additional "expander" programmable P-terms which do not directly feed a fixed device. Relatively simple logic functions can be performed by suitably programming the P-terms feeding the fixed devices. More complex logic functions can be performed by suitably programming the required number of expander P-terms, and then combining the outputs of those P-terms by means of another P-term. In addition, a programmable interconnect array is provided to allow certain inputs to the device to be applied to any programmable portion of the device, and also to allow the outputs of at least one of the fixed devices to be also applied to any programmable portion of the device.
摘要翻译：具有相对较少数量的可编程产品术语（“P项”）供给每个固定组合逻辑器件的可编程逻辑器件，以及不直接馈送固定器件的附加“扩展器”可编程P项。可以通过对馈送固定设备的P项进行适当编程来执行相对简单的逻辑功能。可以通过适当地编程所需数量的扩展器P项来执行更复杂的逻辑功能，然后通过另外的P项组合这些P项的输出。此外，提供可编程互连阵列以允许将装置的某些输入施加到装置的任何可编程部分，并且还允许至少一个固定装置的输出也被施加到装置的任何可编程部分装置。

6. 发明授权

US4871930A Programmable logic device with array blocks connected via programmable interconnect 失效
标题翻译：具有可编程互连连接的阵列模块的可编程逻辑器件
公开(公告)号：US4871930A
公开(公告)日：1989-10-03
申请号：US190663
申请日：1988-05-05
申请人： Sau-Ching Wong , Hock-Chuen So , Stanley J. Kopec, Jr. , Robert F. Hartmann
发明人： Sau-Ching Wong , Hock-Chuen So , Stanley J. Kopec, Jr. , Robert F. Hartmann
IPC分类号： H01L21/82 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728 , H01L2224/05554 , H01L2224/49113
摘要： A programmable logic device having a relatively small number of programmable product terms ("P-terms") feeding each fixed combinatorial logic device, and additional "expander" programmable P-terms which do not directly feed a fixed device. Relatively simple logic functions can be performed by suitably programming the P-terms feeding the fixed devices. More complex logic functions can be performed by suitably programming the required number of expander P-terms, and then combining the outputs of those P-terms by means of another P-term. In addition, a programmable interconnect array is provided to allow certain inputs to the device to be applied to any programmable portion of the device, and also to allow the outputs of at least one of the fixed devices to be also applied to any programmable portion of the device.

7. 发明授权

US4899067A Programmable logic devices with spare circuits for use in replacing defective circuits 失效
标题翻译：具有备用电路的可编程逻辑器件用于更换有缺陷的电路
公开(公告)号：US4899067A
公开(公告)日：1990-02-06
申请号：US222832
申请日：1988-07-22
申请人： Hock-Chuen So , Sau-Ching Wong
发明人： Hock-Chuen So , Sau-Ching Wong
IPC分类号： H03K19/177 , G06F11/20
CPC分类号： H03K19/17748 , H03K19/17736 , H03K19/17764
摘要： A programmable logic device having a plurality of word lines and a plurality of bit lines, each of which is programmably interconnectable to at least one of the word lines for producing on each bit line a signal which is a logical function of the signal or signals on the word line or lines to which that bit line is interconnected. The logic device further includes at least one spare word line and/or bit line for use in the event that one of the regular lines of the same kind in defective. When the spare line is to be used, the device is preprogrammed to automatically redirect all signals intended for the bad line to another line, thereby putting the spare line into use. The signals thus automatically redirected include both the signals used during program mode to selectively interconnect the word lines and bit lines and the data signals subsequently processed during normal operation of the device.

8. 发明授权

US6157558A Content addressable memory cell and array architectures having low transistor counts 失效
标题翻译：具有低晶体管数量的内容寻址存储单元和阵列结构
公开(公告)号：US6157558A
公开(公告)日：2000-12-05
申请号：US316499
申请日：1999-05-21
申请人： Sau-Ching Wong
发明人： Sau-Ching Wong
IPC分类号： G11C15/04 , G11C15/00
CPC分类号： G11C15/04
摘要： An SRAM-based CAM cell and CAM array architecture reduce transistor count and memory size by replacing pass transistors and search transistors of conventional SRAM-base CAM cells with a pair of transistors having gates coupled to bit lines. The two bit-line-controlled transistors in a CAM cell are between storage nodes and a word/match line for the CAM cell. The sizes of pull-up and pull-down devices in the CAM cells are selected so that grounding a storage node to a word/match line through one of the two bit-line-controlled transistors can change the bit stored in a CAM cell, but applying a voltage (near the supply voltage) from the word/match line through either of the two bit-line-controlled transistors to a storage node cannot change the bit or data stored in a CAM cell. Accordingly, a write operation grounds a selected word/match line and applies a voltage to the unselected word/match lines. A search operation charges all word/match lines and senses the word/match lines. Addition of a mask element that controls the connection of the CAM cell to the word/match line can convert a binary CAM architecture to a ternary CAM architecture. The mask element optionally includes circuitry that causes the mask element to power up in a known state. Within the ternary CAM cell, a bypass transistor can be provide to bypass the effect of the mask element and facilitate write operations or temporarily suspend local masking.
摘要翻译：基于SRAM的CAM单元和CAM阵列架构通过用具有耦合到位线的栅极的一对晶体管代替传统晶体管和搜索常规SRAM基底CAM单元的晶体管来减少晶体管数量和存储器大小。 CAM单元中的两个位线控制晶体管位于存储节点和CAM单元的字/匹配线之间。选择CAM单元中的上拉和下拉装置的大小，使得通过两个位线控制的晶体管之一将存储节点接地到字/匹配线可以改变存储在CAM单元中的位，但是通过两个位线控制晶体管中的任何一个将字/匹配线施加电压（靠近电源电压）到存储节点不能改变存储在CAM单元中的位或数据。因此，写入操作使所选择的字/匹配线接合并且向未选择的字/匹配线施加电压。搜索操作对所有字/匹配线进行充电并感测字/匹配线。控制CAM单元与单词/匹配线的连接的掩码元素的添加可将二进制CAM架构转换为三元CAM架构。掩模元件可选地包括使掩模元件在已知状态下加电的电路。在三元CAM单元内，可以提供旁路晶体管来绕过掩模元件的效果，并且便于写操作或暂时暂停本地掩蔽。

9. 发明授权

US06363008B1 Multi-bit-cell non-volatile memory with maximized data capacity 有权
标题翻译：具有最大数据容量的多位单元非易失性存储器
公开(公告)号：US06363008B1
公开(公告)日：2002-03-26
申请号：US09505519
申请日：2000-02-17
申请人： Sau-Ching Wong
发明人： Sau-Ching Wong
IPC分类号： G11C1604
CPC分类号： G11C16/20 , G11C11/56 , G11C11/5621 , G11C2211/5641
摘要： A multiple-bit-per-cell memory includes multiple memory arrays, where the number of bits stored per cell is separately set for each of the memory arrays. Memory arrays that testing proves are accurate when writing, storing, and reading a larger number of bits per cell are set to store more bits per cell, and memory arrays that cannot accurately write, store, or read as many bits per cell are set to store fewer bits per cell. Accordingly, the setting of the numbers of bits per cell for the respective memory arrays can maximize the capacity of a memory when some arrays perform better than expected. When the memory arrays on average perform worse than expected, the setting of the numbers of bits per cell salvage the memory device even if the memory is unable to provide the total expected memory capacity. One implementation of the memory includes a register for the settings of the memory arrays and one or more analog/multi-level write and read circuits. One or more converters convert between the analog and digital signals where the digital signals contain a number of bits selected according to a memory array being accessed. A data buffer between the arrays and a data input/output interface collects data for conversion between the variable data sizes used in the memory and standard size data units input and output from the memory.
摘要翻译：多单元存储器包括多个存储器阵列，其中每个存储器阵列分别设置每个存储单元存储的位数。当每个单元写入，存储和读取更多的位数时，测试证明的存储器阵列是准确的，以便存储每个单元更多的位，并且不能准确地写入，存储或读取每个单元的位数的存储器阵列被设置为每个单元存储更少的位。因此，当一些阵列执行得比预期的更好时，各个存储器阵列的每个单元的比特数的设置可以最大化存储器的容量。当存储器阵列平均执行得比预期差时，即使存储器不能提供总预计的存储器容量，每个单元的比特数的设置也能够对存储器件进行补救。存储器的一个实现包括用于存储器阵列和一个或多个模拟/多电平写入和读取电路的设置的寄存器。一个或多个转换器在模拟信号和数字信号之间转换，其中数字信号包含根据正被存取的存储器阵列选择的位数。阵列和数据输入/输出接口之间的数据缓冲区收集用于在存储器中使用的可变数据大小和从存储器输入和输出的标准尺寸数据单元之间进行转换的数据。

10. 发明授权

US6166938A Data encoding for content addressable memories 失效
标题翻译：内容可寻址存储器的数据编码
公开(公告)号：US6166938A
公开(公告)日：2000-12-26
申请号：US315807
申请日：1999-05-21
申请人： Sau-Ching Wong
发明人： Sau-Ching Wong
IPC分类号： G11C15/04 , G11C15/00
CPC分类号： G11C15/043 , G11C15/046
摘要： Input partitioning logic is coupled to bit-lines of a content addressable memory (CAM) array having four-transistor (4-T) non-volatile Flash CAM cells. Prior to a program or search operation on the 4-T Flash CAM cells, two input data bits and their complements are applied to the input partitioning logic, which can be two-input NAND, NOR, AND, or OR gates. By selecting the appropriate values for the input bits, individual ones of the memory cells in the 4-T CAM cell can be programmed, or a desired two-bit pattern can be searched. The use of input partitioning logic prior to applying the search and program voltages to the bit-lines of the CAM cell results in substantially less voltage transitions during searches and less required programming current because fewer Flash memory cells are required to be programmed. Consequently, power consumption while operating the CAM array is substantially reduced, and the Flash memory cell endurance is effectively increased. Global masking techniques can be effectively applied to the input partitioning logic. These same techniques can also be used for DRAM-based CAM cells.
摘要翻译：输入分区逻辑耦合到具有四晶体管（4-T）非易失性闪存CAM单元的内容可寻址存储器（CAM）阵列的位线。在4-T Flash CAM单元的程序或搜索操作之前，将两个输入数据位及其补码应用于输入分区逻辑，其可以是双输入NAND，NOR，AND或或门。通过为输入位选择合适的值，可以对4-T CAM单元中的单个存储单元进行编程，或者可以搜索所需的两位模式。在将搜索和编程电压施加到CAM单元的位线之前使用输入分区逻辑导致在搜索期间实质上更少的电压转换和较少需要的编程电流，因为需要编程更少的闪存单元。因此，大大减少了操作CAM阵列时的功耗，并且有效地提高了闪存单元的耐久性。全局掩蔽技术可以有效地应用于输入分区逻辑。这些相同的技术也可以用于基于DRAM的CAM单元。

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