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1. 发明授权

US07397697B2 Multi-bit-per-cell flash EEPROM memory with refresh 有权
标题翻译：多单元快闪EEPROM存储器刷新
公开(公告)号：US07397697B2
公开(公告)日：2008-07-08
申请号：US11620127
申请日：2007-01-05
申请人： Hock C. So , Sau C. Wong
发明人： Hock C. So , Sau C. Wong
IPC分类号： G11C16/06
CPC分类号： G06F11/1072 , B64C27/006 , G01N29/14 , G01N29/227 , G06F11/106 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/04 , G11C16/10 , G11C16/3418 , G11C16/3431 , G11C16/3459 , G11C29/00 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C2211/5634
摘要： A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process checks whether a threshold voltage is in a forbidden zone. Alternately, a refresh process includes reprogramming the threshold voltage into an allowed state. In the case of a flash memory, a refresh reads a sector of the memory and saves corrected data from the sector in a buffer or another sector. The corrected data from the buffer or other sector can be written back in the original sector, or the corrected data can be left in the other sector with addresses of the original sector being mapped to the other sector. Refresh process for the non-volatile memory can be performed in response to detecting a threshold voltage in a forbidden zone or periodically.
摘要翻译：多单元单元非易失性存储器将存储器单元的适当阈值电压划分为对应于用于存储数据的允许状态的范围和对应于指示数据错误的禁止区域的范围。读取过程检查阈值电压是否在禁止区域。或者，刷新过程包括将阈值电压重新编程为允许状态。在闪速存储器的情况下，刷新读取存储器的扇区，并将来自扇区的校正数据保存在缓冲器或另一扇区中。来自缓冲器或其他扇区的校正数据可以被写回到原始扇区中，或者校正的数据可以留在另一扇区中，原始扇区的地址映射到另一个扇区。可以响应于检测到禁止区域中的阈值电压或周期性地执行用于非易失性存储器的刷新处理。

2. 发明授权

US06556465B2 Adjustable circuits for analog or multi-level memory 失效
公开(公告)号：US06556465B2
公开(公告)日：2003-04-29
申请号：US10109353
申请日：2002-03-27
申请人： Andreas M. Haeberli , Sau C. Wong , Hock C. So , Carl W. Werner , Cheng-Yuan Michael Wang , Leon Sea Jiunn Wong
发明人： Andreas M. Haeberli , Sau C. Wong , Hock C. So , Carl W. Werner , Cheng-Yuan Michael Wang , Leon Sea Jiunn Wong
IPC分类号： G11C2700
CPC分类号： G11C11/5642 , G11C5/145 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C16/12 , G11C16/30 , G11C16/32 , G11C27/005 , G11C27/02 , G11C27/026
摘要： An integrated circuit detects the voltage level of the supply voltage to the integrated circuit. Circuity on the integrated circuit including the charge pump circuity adjusts to operate more effectively or efficiently at the voltage level of the supply voltage.

3. 发明授权

US06370075B1 Charge pump circuit adjustable in response to an external voltage source 有权
标题翻译：电荷泵电路响应于外部电压源可调
公开(公告)号：US06370075B1
公开(公告)日：2002-04-09
申请号：US09343206
申请日：1999-06-29
申请人： Andreas M. Haeberli , Sau C. Wong , Hock C. So , Carl W. Werner , Cheng-Yuan Michael Wang , Leon Sea Jiunn Wong
发明人： Andreas M. Haeberli , Sau C. Wong , Hock C. So , Carl W. Werner , Cheng-Yuan Michael Wang , Leon Sea Jiunn Wong
IPC分类号： G11C700
CPC分类号： G11C11/5642 , G11C5/145 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C16/12 , G11C16/30 , G11C16/32 , G11C27/005 , G11C27/02 , G11C27/026
摘要： An integrated circuit detects the voltage level of the supply voltage to the integrated circuit. Circuity on the integrated circuit including the charge pump circuity adjusts to operate more effectively or efficiently at the voltage level of the supply voltage.
摘要翻译：集成电路检测到集成电路的电源电压的电平。包括电荷泵电路在内的集成电路的电流调整为在电源电压的电压电平下更有效或更有效地工作。

4. 发明授权

US06278633B1 High bandwidth flash memory that selects programming parameters according to measurements of previous programming operations 有权
标题翻译：高带宽闪存，根据以前的编程操作的测量选择编程参数
公开(公告)号：US06278633B1
公开(公告)日：2001-08-21
申请号：US09434588
申请日：1999-11-05
申请人： Sau C. Wong , Hock C. So
发明人： Sau C. Wong , Hock C. So
IPC分类号： G11C1134
CPC分类号： G11C29/02 , G11C7/1039 , G11C11/5621 , G11C11/5628 , G11C16/10 , G11C29/021 , G11C29/028
摘要： A multi-level non-volatile memory includes one or more arrays of memory cells including storage cells and dummy cells. The memory observes or measures write operations that write dummy values to the dummy cells and from the observations or measurements selects parameters such as programming voltages or the duration of program cycles. The selection of parameters optimizes write precision within the available access time of a high bandwidth memory. Accessing dummy cells also allows the memory to reach a steady state before writing or reading of data begins. In particular, multiple pipelines sequentially start write operations, and writing of data begins when an equilibrium number of pipelines are performing write operations. Similarly, multiple read operation start before the reading of data for actual use. The stabilization is particularly critical when the pipelines share a power source.
摘要翻译：多级非易失性存储器包括一个或多个存储单元阵列，包括存储单元和虚拟单元。存储器观察或测量写入虚拟值到虚拟单元的写入操作，并且从观测或测量中选择诸如编程电压或编程周期的持续时间的参数。参数的选择可以在高带宽内存的可用访问时间内优化写入精度。访问虚拟单元还允许存储器在写入或读取数据开始之前达到稳定状态。特别地，多个管道顺序地开始写入操作，并且当平衡数量的管线正在执行写入操作时开始写入数据。类似地，在读取实际使用的数据之前开始多次读取操作。当管道共享电源时，稳定性尤其重要。

5. 发明授权

US06151246A Multi-bit-per-cell flash EEPROM memory with refresh 有权
公开(公告)号：US06151246A
公开(公告)日：2000-11-21
申请号：US200220
申请日：1998-11-25
申请人： Hock C. So , Sau C. Wong
发明人： Hock C. So , Sau C. Wong
IPC分类号： G11C16/02 , B64C27/00 , G01N29/14 , G01N29/22 , G06F11/10 , G11C11/56 , G11C16/06 , G11C29/42 , G11C29/50
CPC分类号： G06F11/1072 , B64C27/006 , G01N29/14 , G01N29/227 , G06F11/106 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/3418 , G11C16/3431 , G11C16/3459 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C16/04 , G11C2211/5634 , G11C29/00
摘要： A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In an alternative embodiment, a refresh process includes reprogramming the threshold voltage into an allowed state. In the case of a flash memory, a refresh reads a sector of the memory and saves corrected data from the sector in a buffer or another sector. The corrected data from the buffer or other sector can be written back in the original sector, or the corrected data can be left in the other sector with addresses of the original sector being mapped to the other sector. Refresh process for the non-volatile memory can be perform in response to detecting a threshold voltage in a forbidden zone, as part of a power-up procedure for the memory, or periodically with a period on the order of days, weeks, or months. As a further aspect, the allowed states correspond to gray coded digital values so that allowed states that are adjacent in threshold voltage correspond to multibit values that differ in only a single bit. Error detection and correction codes can be used to identify data errors and generate corrected data for refresh operations.

6. 发明授权

US5969986A High-bandwidth read and write architectures for non-volatile memories 失效
标题翻译：用于非易失性存储器的高带宽读写架构
公开(公告)号：US5969986A
公开(公告)日：1999-10-19
申请号：US103623
申请日：1998-06-23
申请人： Sau C. Wong , Hock C. So
发明人： Sau C. Wong , Hock C. So
IPC分类号： G11C16/06 , G06F12/00 , G06F12/06 , G11C7/10 , G11C11/56 , G11C16/00 , G11C16/10 , G11C16/26 , G11C27/00 , G11C27/02 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C27/005 , G11C27/026 , G11C7/1039 , G11C16/32 , G11C27/02
摘要： A memory architecture for a non-volatile analog or multiple-bits-per-cell memory includes multiple separate memory arrays and multiple read/write pipelines. The multiple read/write pipelines share a read circuit and/or a write circuit to reduce the circuit area of each pipeline and the circuit area of the memory as a whole. In one embodiment, a shared write circuit generates a programming voltage that changes with an input signal representing values to be written to the memory. Each pipeline includes a sample-and-hold circuit that samples the programming voltage when the pipeline begins a write operation. The write circuit can additionally generate a verify voltage that a second sample-and-hold circuit in each pipeline samples when starting a write operation. In another embodiment, a shared read circuit generates a read signal that ramps across the range of permitted threshold voltages for the memory cells, and a sense amplifier in each pipeline clocks a sample-and-hold circuit or another temporary storage circuit when the sense amplifier senses a transition in conductivity of a selected memory cell. When clocked, the sample-and-hold circuit or other temporary storage circuit registers a signal that corresponds to the read signal and indicates a data value associated with the voltage of the read signal. In alternative embodiments, the signal registered is the read signal, a converted form of the read signal, or a multi-bit digital signal.
摘要翻译：用于非易失性模拟或多位单元存储器的存储器架构包括多个单独的存储器阵列和多个读/写管线。多个读/写管线共享读电路和/或写电路，以减少每个管线的电路面积和整个存储器的电路面积。在一个实施例中，共享写入电路产生用表示要写入存储器的值的输入信号改变的编程电压。每个流水线包括采样保持电路，用于在管线开始写操作时对编程电压进行采样。写入电路还可以产生在开始写入操作时每个流水线中的第二个采样和保持电路采样的验证电压。在另一个实施例中，共享读取电路产生斜坡跨越存储器单元的允许阈值电压范围的读取信号，并且每个流水线中的读出放大器对采样保持电路或另一个临时存储电路进行时钟，当读出放大器感测所选存储器单元的电导率的转变。当采样时，采样保持电路或其他临时存储电路注册与读取信号相对应的信号，并指示与读取信号的电压相关联的数据值。在替代实施例中，登记的信号是读取信号，读取信号的转换形式或多位数字信号。

7. 发明授权

US5128565A Sense amplifier with increased speed and reduced power consumption 失效
标题翻译：感应放大器具有增加的速度和降低的功耗
公开(公告)号：US5128565A
公开(公告)日：1992-07-07
申请号：US596764
申请日：1990-10-12
申请人： Cameron McClintock , Hock C. So
发明人： Cameron McClintock , Hock C. So
IPC分类号： G11C7/06 , H03K17/00 , H03K17/0416
CPC分类号： H03K17/04163 , G11C7/065 , G11C7/067 , H03K2217/0036
摘要： In a programmable logic device sense amplifier, switching speed is increased and quiescent power consumption is decreased by incorporating an auxiliary high-speed circuit which assists the sense amplifier to charge the parasitic capacitance of the output node during, and for a short time after, that node's low-to-high voltage transitions. The auxiliary circuit presents a high resistance to the output node at times other than during and shortly after low-to-high transitions, and therefore does not affect the operation of the sense amplifier at these other times. The sense amplifier can be operated in single-ended bit line mode in complementary bit line mode.
摘要翻译：在可编程逻辑器件读出放大器中，通过结合辅助高速电路来增加开关速度并降低静态功耗，该辅助高速电路有助于读出放大器对输出节点的寄生电容进行充电，并在短时间之后节点的低电压到高电压转换。辅助电路在低到高转换之后和之后的时间内对输出节点呈现高电阻，因此在这些其他时间不影响读出放大器的工作。在互补位线模式下，读出放大器可以在单端位线模式下工作。

8. 发明授权

US07554844B2 Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency 有权
标题翻译：具有模拟或多电平存储单元的集成电路和用户可选择的采样频率
公开(公告)号：US07554844B2
公开(公告)日：2009-06-30
申请号：US11876093
申请日：2007-10-22
申请人： Carl W. Werner , Andreas M. Haeberli , Leon Sea Jiunn Wong , Cheng-Yuan Michael Wang , Hock C. So , Sau C. Wong
发明人： Carl W. Werner , Andreas M. Haeberli , Leon Sea Jiunn Wong , Cheng-Yuan Michael Wang , Hock C. So , Sau C. Wong
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C5/145 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C16/12 , G11C16/30 , G11C16/32 , G11C27/005 , G11C27/02 , G11C27/026
摘要： Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.
摘要翻译：技术用于在诸如集成电路的存储器单元的介质中存储信息，并且还从介质检索信息。集成电路包括能够进行多电平或模拟电压电平存储的非易失性存储单元（416）。集成电路可以以模拟或数字形式或两者存储或记录信息。使用用户选择的采样频率将信息存储在集成电路中并从集成电路检索。用户对采样频率的选择存储在集成电路内。

9. 发明授权

US06345000B1 Flash memory permitting simultaneous read/write and erase operations in a single memory array 有权
标题翻译：闪存允许在单个存储器阵列中同时进行读/写和擦除操作
公开(公告)号：US06345000B1
公开(公告)日：2002-02-05
申请号：US09199971
申请日：1998-11-25
申请人： Sau C. Wong , Hock C. So , Cheng-Yuan Michael Wang , Roger Ying Kuen Lo
发明人： Sau C. Wong , Hock C. So , Cheng-Yuan Michael Wang , Roger Ying Kuen Lo
IPC分类号： G11C1604
CPC分类号： G11C16/08 , G11C16/10 , G11C16/16
摘要： A non-volatile Flash memory simultaneously performs an erase operation and a write or read operation in the same array of memory cells. The memory has a row based sector architecture, i.e., sectors that contain one or more complete rows of memory cells. During an erase operation, an erase voltage applied to the source lines for one or more rows corresponding to a sector does not affect write or read operations being performed in other sectors, i.e., other rows. Similarly, voltages applied to row lines for access to a memory cell have no effect on the erase operation being performed in another sector. A column line voltage applied for access to a memory cell has little affect on the erase operation. The memory can implement a look-ahead erase for a continuous reading or writing operation.
摘要翻译：非易失性闪存同时在相同的存储单元阵列中执行擦除操作和写或读操作。存储器具有基于行的扇区架构，即，包含一行或多行完整存储器单元的扇区。在擦除操作期间，施加到对应于扇区的一行或多行的源极线的擦除电压不影响在其它扇区即其它行中正在执行的写入或读取操作。类似地，施加到行线以访问存储器单元的电压对在另一扇区中执行的擦除操作没有影响。施加到存储单元的列线电压对擦除操作几乎没有影响。存储器可以实现用于连续读取或写入操作的先行擦除。

10. 发明授权

US06330185B1 High bandwidth multi-level flash memory using dummy memory accesses to improve precision when writing or reading a data stream 有权
标题翻译：使用虚拟内存访问的高带宽多级闪存可以在写入或读取数据流时提高精度
公开(公告)号：US06330185B1
公开(公告)日：2001-12-11
申请号：US09768922
申请日：2001-01-23
申请人： Sau C. Wong , Hock C. So
发明人： Sau C. Wong , Hock C. So
IPC分类号： G11C1134
CPC分类号： G11C29/02 , G11C7/1039 , G11C11/5621 , G11C11/5628 , G11C16/10 , G11C29/021 , G11C29/028
摘要： A multi-level non-volatile memory includes one or more arrays of memory cells including storage cells and dummy cells. The memory observes or measures write operations that write dummy values to the dummy cells and from the observations or measurements selects parameters such as programming voltages or the duration of program cycles. The selection of parameters optimizes write precision within the available access time of a high bandwidth memory. Accessing dummy cells also allows the memory to reach a steady state before writing or reading of data begins. In particular, multiple pipelines sequentially start write operations, and writing of data begins when an equilibrium number of pipelines are performing write operations. Similarly, multiple read operation start before the reading of data for actual use. The stabilization is particularly critical when the pipelines share a power source.
摘要翻译：多级非易失性存储器包括一个或多个存储单元阵列，包括存储单元和虚拟单元。存储器观察或测量写入虚拟值到虚拟单元的写入操作，并且从观测或测量中选择诸如编程电压或编程周期的持续时间的参数。参数的选择可以在高带宽内存的可用访问时间内优化写入精度。访问虚拟单元还允许存储器在写入或读取数据开始之前达到稳定状态。特别地，多个管道顺序地开始写入操作，并且当平衡数量的管线正在执行写入操作时开始写入数据。类似地，在读取实际使用的数据之前开始多次读取操作。当管道共享电源时，稳定性尤其重要。

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