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1. 发明授权

US4609986A Programmable logic array device using EPROM technology 失效
标题翻译：可编程逻辑阵列器件采用EPROM技术
公开(公告)号：US4609986A
公开(公告)日：1986-09-02
申请号：US620451
申请日：1984-06-14
申请人： Robert F. Hartmann , Yiu-Fai Chan , Robert Frankovich , Jung-Hsing Ou
发明人： Robert F. Hartmann , Yiu-Fai Chan , Robert Frankovich , Jung-Hsing Ou
IPC分类号： G11C17/00 , G11C11/40 , G11C16/04 , H03K19/177 , G06F7/38
CPC分类号： H03K19/17712 , H03K19/17716
摘要： An electrically programmable, eraseable and reprogrammable, monolithic integrated circuit logic array device is disclosed. The device includes a plurality of three types of logic array macrocells, each including an AND array matrix of EPROM transistors configured to form a plurality of "product terms" which are fed into another matrix comprised of "OR" gates, the outputs of which form sum-of-products expressions of the inputs to the AND arrays. Also contained in the macrocells are simple EPROM transistors which, when combined with other appropriate circuitry, form control elements, a plurality of storage registers (D flip-flops), feedback drivers, input drivers and output drivers, all integrated on the same substrate. The input drivers and feedback drivers provide input signals to the AND arrays and the outputs from the D flip-flops can be directed to either the feedback drivers or the output drivers. Control of data sources and destinations is determined by the control elements which in turn are determined by single EPROM transistors. Thus, the architecture as well as the logic function is programmable.
摘要翻译：公开了电可编程，可擦除和可编程的单片集成电路逻辑阵列器件。该装置包括多个三种类型的逻辑阵列宏单元，每个宏单元包括被配置成形成多个“乘积项”的EPROM晶体管的AND阵列矩阵，其被馈送到由“OR”门组成的另一个矩阵中，其输出形式 AND数组输入的产品总和表达式。宏单元中还包含简单的EPROM晶体管，当与其它合适的电路组合时，它们形成控制元件，多个存储寄存器（D触发器），反馈驱动器，输入驱动器和输出驱动器，它们都集成在同一衬底上。输入驱动器和反馈驱动器为AND阵列提供输入信号，D触发器的输出可以被引导到反馈驱动器或输出驱动器。数据源和目的地的控制由控制元件确定，控制元件又由单个EPROM晶体管确定。因此，架构以及逻辑功能是可编程的。

2. 发明授权

US5159352A Dynamic focusing system for use with discontinuous medium 失效
标题翻译：用于不连续介质的动态聚焦系统
公开(公告)号：US5159352A
公开(公告)日：1992-10-27
申请号：US821177
申请日：1992-01-15
申请人： Guillermo S. Ferla , Walter P. Haimberger , Robert F. Hartmann
发明人： Guillermo S. Ferla , Walter P. Haimberger , Robert F. Hartmann
IPC分类号： B41J2/44 , B41J2/45 , G03F1/00 , H04N1/036 , H04N1/047 , H04N1/06 , H04N1/08 , H04N1/23
CPC分类号： B41J19/20 , B41J2/45 , H04N1/036 , H04N1/0473 , H04N1/08 , H04N1/0813 , H04N1/06 , H04N2201/0471 , H04N2201/04755 , H04N2201/04786
摘要： A printing system employs a rotating drum for carrying a photosensitive printing medium in the form of a discontinuous sheet, there being a clamp carried by the drum and rotating therewith for holding ends of the sheet to secure the sheet to the drum. The system includes a print head having a laser beam which is spatially and temporally modulated for gray-scale printing of individual pixels of an image. The head is scanned parallel to an axis of the drum. A servomechanism responsive to angular orientation of the drum produces a linear scan during rotation of the drum. An optical system within the head provides a common path through a common objective lens for both a write laser beam and for a focus laser beam of an automatic focusing apparatus which positions the objective lens rapidly by a dither motion to compensate for undulations in the surface of the print medium. The objective lens is carried at a reference position during passage of the clamp, the reference position being updated periodically by measurements of focus.
摘要翻译：打印系统采用旋转滚筒来承载不连续薄片形式的光敏打印介质，由滚筒承载的夹具与其一起旋转以保持薄片的端部以将薄片固定到滚筒上。该系统包括具有激光束的打印头，其被空间和时间调制以用于图像的各个像素的灰度打印。头部平行于滚筒的轴线扫描。响应于滚筒的角度定向的伺服机构在滚筒旋转期间产生线性扫描。头部内的光学系统提供通过用于写入激光束和自动聚焦装置的聚焦激光束的公共物镜的公共路径，其通过抖动运动快速定位物镜，以补偿物镜的表面中的起伏打印介质。物镜在夹具通过期间在参考位置承载，参考位置通过焦点测量周期性地更新。

3. 发明授权

US4713792A Programmable macrocell using eprom or eeprom transistors for architecture control in programmable logic circuits 失效
标题翻译：可编程宏单元使用eprom或eeprom晶体管进行可编程逻辑电路中的架构控制
公开(公告)号：US4713792A
公开(公告)日：1987-12-15
申请号：US742089
申请日：1985-06-06
申请人： Robert F. Hartmann , Yiu-Fai Chan , Robert J. Frankovich , Jung-Hsing Ou , Hock C. So , Sau-Ching Wong
发明人： Robert F. Hartmann , Yiu-Fai Chan , Robert J. Frankovich , Jung-Hsing Ou , Hock C. So , Sau-Ching Wong
IPC分类号： G11C17/00 , G11C16/04 , H01L21/82 , H01L21/8247 , H01L29/788 , H01L29/792 , H03K17/693 , H03K19/173 , H03K19/177 , G06F1/00
CPC分类号： H03K19/1736 , H03K17/693 , H03K19/1737
摘要： A programmable macrocell 28 for use in an integrated circuit device including an electronic circuit 32 responsive to control signals and operative to perform particular operations selected by the control signals on input data signals and to develop commensurate output signals, and one or more architecture control circuits 30 each including a programmable EPROM device 34 which when programmed generates a logic signal of a first state and when unprogrammed generates a logic signal of a second state, a read and write control circuit 36 responsive to input program data signals and a corresponding address signal and operative to program the EPROM device 34 by applying a programming potential thereto, and a sensing circuit 38 for sensing the programmed or unprogrammed status of the EPROM device 34 and for developing a commensurate control signal for input to the electronic circuit 32.
摘要翻译：一种用于集成电路设备的可编程宏单元28，其包括响应于控制信号的电子电路32，并且可操作以执行由输入数据信号上的控制信号选择的特定操作并且开发相应的输出信号，以及一个或多个架构控制电路30 每个都包括一个可编程EPROM器件34，当被编程时产生第一状态的逻辑信号，并且当未编程产生第二状态的逻辑信号时，读和写控制电路36响应输入的程序数据信号和对应的地址信号，通过向其施加编程电位来对EPROM器件34进行编程;以及感测电路38，用于感测EPROM器件34的编程状态或未编程状态，并用于形成相应的控制信号以输入到电子电路32。

4. 发明授权

US4871930A Programmable logic device with array blocks connected via programmable interconnect 失效
标题翻译：具有可编程互连连接的阵列模块的可编程逻辑器件
公开(公告)号：US4871930A
公开(公告)日：1989-10-03
申请号：US190663
申请日：1988-05-05
申请人： Sau-Ching Wong , Hock-Chuen So , Stanley J. Kopec, Jr. , Robert F. Hartmann
发明人： Sau-Ching Wong , Hock-Chuen So , Stanley J. Kopec, Jr. , Robert F. Hartmann
IPC分类号： H01L21/82 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728 , H01L2224/05554 , H01L2224/49113
摘要： A programmable logic device having a relatively small number of programmable product terms ("P-terms") feeding each fixed combinatorial logic device, and additional "expander" programmable P-terms which do not directly feed a fixed device. Relatively simple logic functions can be performed by suitably programming the P-terms feeding the fixed devices. More complex logic functions can be performed by suitably programming the required number of expander P-terms, and then combining the outputs of those P-terms by means of another P-term. In addition, a programmable interconnect array is provided to allow certain inputs to the device to be applied to any programmable portion of the device, and also to allow the outputs of at least one of the fixed devices to be also applied to any programmable portion of the device.

5. 发明授权

US06232904B1 Scanning system for film recorder 失效
标题翻译：电影录像机扫描系统
公开(公告)号：US06232904B1
公开(公告)日：2001-05-15
申请号：US09471782
申请日：1999-12-23
申请人： Robert F. Hartmann , Patrick J. Hegarty , Timothy R. Crawford , Thomas H Campbell
发明人： Robert F. Hartmann , Patrick J. Hegarty , Timothy R. Crawford , Thomas H Campbell
IPC分类号： H03H168
CPC分类号： H04N3/2335 , H03K4/026 , H04N3/16 , H04N5/257 , H04N5/843
摘要： A scanning system for a film recorder utilizes multiple digital-to-analog converters (DACs) to produce a linear output for a vertical deflection circuit which drives a vertical yoke circuit for controlling a CRT beam in a film recorder. The system contains a coarse DAC, a fine DAC, and a delta DAC which provides a signal representing the analog change from line to line. A summing circuit, a difference amplifier, a A/D converter, and a calibration sequence controlled by a DSP create a table to effectively increase the resolution and linearity of the deflection output signal.
摘要翻译：用于胶片记录器的扫描系统利用多个数模转换器（DAC）来产生垂直偏转电路的线性输出，该垂直偏转电路驱动用于控制胶片记录器中的CRT光束的垂直磁轭电路。该系统包含一个粗略的DAC，一个精细的DAC和一个增量DAC，它提供一个表示一行到另一个模拟变化的信号。由DSP控制的求和电路，差分放大器，A / D转换器和校准序列产生一个表，以有效提高偏转输出信号的分辨率和线性度。

6. 发明授权

US4774421A Programmable logic array device using EPROM technology 失效
标题翻译：可编程逻辑阵列器件采用EPROM技术
公开(公告)号：US4774421A
公开(公告)日：1988-09-27
申请号：US907075
申请日：1986-09-12
申请人： Robert F. Hartmann , Sau-Ching Wong , Yiu-Fai Chan , Jung-Hsing Ou
发明人： Robert F. Hartmann , Sau-Ching Wong , Yiu-Fai Chan , Jung-Hsing Ou
IPC分类号： H03K5/02 , H03K17/693 , H03K19/094 , H03K19/173 , H03K19/177
CPC分类号： H03K17/693 , H03K19/09425 , H03K19/1736 , H03K19/1737 , H03K19/17712 , H03K5/023
摘要： A programmable logic array device basically comprising a programmable AND gate array (FIGS. 5, 11) having addressable rows (40-45) and columns (32-38) or memory cells (30, 31) which can be individually programmed to represent logic data; an input signal receiving circuit (FIG. 9) for developing a corresponding buffered input signal; a first row driver (FIG. 10) responsive to the buffered signal and operative to cause a particular row of memory cells in an AND array (FIG. 11) to output corresponding logical product of AND-input signals, OR/NOR sensing circuitry (FIG. 12) for sensing the AND array product signals and for developing therefrom corresponding logical OR sum signals; circuit means output terminal circuitry; output switching circuitry (FIG. 14) responsive to a control signal and operative to couple either the circuit means output signal or a registered (FIG. 13) output to a device input or output terminal (FIG. 16); feedback switching circuitry similarly responsive to a control signal and operative to couple either the circuit means output signal, registered output signal, or feedback signal to a row driver; and Reprogrammable Architecture control circuitry (FIG. 24) to provide control signals to said switching circuitry. The device has the advantages of increased density of useable logic functions, and decreased power consumption.
摘要翻译：可编程逻辑阵列器件基本上包括具有可寻址行（40-45）和列（32-38）或存储器单元（30,31）的可编程与门阵列（图5,11），其可以被单独编程以表示逻辑数据; 输入信号接收电路（图9），用于开发相应的缓冲输入信号; 第一行驱动器（图10），响应于缓冲的信号并且可操作以使AND阵列（图11）中的特定行的存储器单元输出对应的AND输入信号的逻辑积OR / NOR感测电路（图12），用于感测AND阵列产品信号并用于从其产生相应的逻辑或和信号; 电路表示输出端子电路; 输出切换电路（图14），响应于控制信号并且可操作地将电路装置输出信号或注册的（图13）输出耦合到设备输入或输出端子（图16）; 反馈切换电路类似地响应于控制信号并且可操作地将电路装置的输出信号，已注册的输出信号或反馈信号耦合到行驱动器; 和可重编程架构控制电路（图24），以向所述开关电路提供控制信号。该器件具有可用逻辑功能密度增加，功耗降低的优点。

7. 发明授权

US5111423A Programmable interface for computer system peripheral circuit card 失效
标题翻译：用于计算机系统外围电路卡的可编程接口
公开(公告)号：US5111423A
公开(公告)日：1992-05-05
申请号：US222565
申请日：1988-07-21
申请人： Stanley J. Kopec, Jr. , Yiu-Fai Chan , Robert F. Hartmann
发明人： Stanley J. Kopec, Jr. , Yiu-Fai Chan , Robert F. Hartmann
IPC分类号： G06F13/14 , G06F12/06
CPC分类号： G06F12/0661
摘要： A programmable interface for a peripheral circuit card is provided. The card is intended for use with a particular computer bus architecture, and the interface can be customized by a user for a particular card design. Instead of designing a custom interface chip, the designer can program one or more programmable logic devices on the interface chip to interface with whatever devices are on the peripheral circuit card.

8. 发明授权

US4912342A Programmable logic device with array blocks with programmable clocking 失效
标题翻译：具有可编程时钟的阵列模块的可编程逻辑器件
公开(公告)号：US4912342A
公开(公告)日：1990-03-27
申请号：US407411
申请日：1989-09-14
申请人： Sau-Ching Wong , Hock-Chuen So , Stanley J. Kopec, Jr. , Robert F. Hartmann
发明人： Sau-Ching Wong , Hock-Chuen So , Stanley J. Kopec, Jr. , Robert F. Hartmann
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/1774 , H01L2224/05554 , H01L2224/49113
摘要： A programmable logic device having a relatively small number of programmable product terms ("P-terms") feeding each fixed combinatorial logic device, and additional "expander" programmable P-terms which do not directly feed a fixed device. Relatively simple logic functions can be performed by suitably programming the P-terms feeding the fixed devices. More complex logic functions can be performed by suitably programming the required number of expander P-terms, and then combining the outputs of those P-terms by means of another P-term. In addition, a programmable interconnect array is provided to allow certain inputs to the device to be applied to any programmable portion of the device, and also to allow the outputs of at least one of the fixed devices to be also applied to any programmable portion of the device.
摘要翻译：具有相对较少数量的可编程产品术语（“P项”）供给每个固定组合逻辑器件的可编程逻辑器件，以及不直接馈送固定器件的附加“扩展器”可编程P项。可以通过对馈送固定设备的P项进行适当编程来执行相对简单的逻辑功能。可以通过适当地编程所需数量的扩展器P项来执行更复杂的逻辑功能，然后通过另外的P项组合这些P项的输出。此外，提供可编程互连阵列以允许将装置的某些输入施加到装置的任何可编程部分，并且还允许至少一个固定装置的输出也被施加到装置的任何可编程部分装置。

9. 发明授权

US4617479A Programmable logic array device using EPROM technology 失效
标题翻译：可编程逻辑阵列器件采用EPROM技术
公开(公告)号：US4617479A
公开(公告)日：1986-10-14
申请号：US607018
申请日：1984-05-03
申请人： Robert F. Hartmann , Sau-Ching Wong , Yiu-Fai Chan , Jung-Hsing Ou
发明人： Robert F. Hartmann , Sau-Ching Wong , Yiu-Fai Chan , Jung-Hsing Ou
IPC分类号： H03K5/02 , H03K19/094 , H03K19/177 , G06F7/00 , H03K19/20
CPC分类号： H03K19/17712 , H03K19/09425 , H03K5/023
摘要： The programmable logic array device basically comprises a programmable AND array (FIGS. 5, 11) having a plurality of memory cells (30, 31) arranged in addressable rows (40-45) and columns (32-38) and which can be individually programmed to contain logic data; an input circuit (FIG. 9) for receiving an input signal and for developing a buffered signal corresponding thereto; a first row driver (FIG. 10) responsive to the buffered signal and operative to interrogate a particular row of the memory cells and to cause the AND array to output signals corresponding to the data contained therein; first sensing circuitry (FIG. 12) for sensing the signals output by the AND array and for developing corresponding data signals which are the logical OR of signals output by the AND array; first output terminal circuitry; and first switching circuitry (FIG. 14) responsive to a control signal and operative to couple the data signal either into the storage circuitry or to the output terminal circuitry (FIG. 16). The device has the advantages generally of greater logic density and lower system power than standard family logic components.
摘要翻译：可编程逻辑阵列器件基本上包括一个可编程AND阵列（图5,11），其具有布置在可寻址行（40-45）和列（32-38）中的多个存储单元（30,31），并且可以单独地编程为包含逻辑数据; 输入电路（图9），用于接收输入信号并用于开发与其对应的缓冲信号; 第一行驱动器（图10），响应于所缓冲的信号并且可操作以询问存储器单元的特定行并使AND阵列输出与其中包含的数据相对应的信号; 第一感测电路（图12），用于感测由AND阵列输出的信号，并用于开发对应的数据信号，该数据信号是由AND阵列输出的信号的逻辑或; 第一输出端子电路; 和第一切换电路（图14），其响应于控制信号并且可操作以将数据信号耦合到存储电路或输出终端电路（图16）。该装置通常具有比标准系列逻辑组件更大的逻辑密度和更低的系统功率的优点。

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