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1. 发明授权

US06429731B2 CMOS voltage divider 有权
标题翻译： CMOS分压器
公开(公告)号：US06429731B2
公开(公告)日：2002-08-06
申请号：US09816934
申请日：2001-03-23
申请人： Thomas Böhm , Robert Esterl , Stefan Lammers , Zoltan Manyoki
发明人： Thomas Böhm , Robert Esterl , Stefan Lammers , Zoltan Manyoki
IPC分类号： G05F1595
CPC分类号： G05F3/242
摘要： A CMOS voltage divider having a first chain containing series-connected MOS transistors of a first conductivity type is described. Each of the MOS transistors have identical geometrical dimensions and, at the same time, each have identical gate-source voltages. The MOS transistors operate in the linear range of their characteristic curve and between opposite ends of the first chain an input voltage to be divided is present and at whose source terminals the voltage fractions can in each case be picked off. Provision is made of a second chain containing series-connected MOS transistors, complementary to the first MOS transistors. The second chain has the same number of transistors as the first MOS transistors and with the same geometrical dimension in each case. The MOS transistors of the first chain are connected to the MOS transistors of the second chain in such a way that each MOS transistor chain generates the gate-source bias voltage for the respective other MOS transistor chain.
摘要翻译：描述了具有包含第一导电类型的串联MOS晶体管的第一链的CMOS分压器。每个MOS晶体管具有相同的几何尺寸，并且同时具有相同的栅源电压。 MOS晶体管在其特性曲线的线性范围内工作，并且在第一链的相对端之间存在待分割的输入电压，并且在每个情况下，其源极端子的电压分数可以被拾取。提供了包含与第一MOS晶体管互补的串联MOS晶体管的第二链。第二链具有与第一MOS晶体管相同数量的晶体管，并且在每种情况下具有相同的几何尺寸。第一链的MOS晶体管以这样的方式连接到第二链的MOS晶体管，使得每个MOS晶体管链为相应的另一个MOS晶体管链产生栅极 - 源极偏置电压。

2. 发明授权

US06574132B2 Circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits 有权
公开(公告)号：US06574132B2
公开(公告)日：2003-06-03
申请号：US09897280
申请日：2001-07-02
申请人： Robert Esterl , Zoltan Manyoki
发明人： Robert Esterl , Zoltan Manyoki
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G11C29/12
摘要： The invention relates to a circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits, where the bit line and the plate line have a voltage equalization transistor provided between them which, in normal operation of the semiconductor circuit, can be switched to low impedance by a control signal in order to equalize the different voltages on the lines.

3. 发明授权

US06236607B1 Integrated memory having a reference potential and operating method for such a memory 失效
标题翻译：具有用于这种存储器的参考电位和操作方法的集成存储器
公开(公告)号：US06236607B1
公开(公告)日：2001-05-22
申请号：US09574701
申请日：2000-05-18
申请人： Tobias Schlager , Zoltan Manyoki , Robert Esterl
发明人： Tobias Schlager , Zoltan Manyoki , Robert Esterl
IPC分类号： G11C702
CPC分类号： G11C11/22
摘要： The memory has a control unit, which, in order to generate a common reference potential on the two bit lines, turns on the first switching element and the selection transistors of the two reference memory cells and, after a specific time period, turns off the selection transistors, while the first switching element remains in the on state and compensates for a potential difference between the two bit lines.
摘要翻译：存储器具有控制单元，为了在两个位线上产生公共参考电位，导通第一开关元件和两个参考存储单元的选择晶体管，并且在特定时间段之后，关断选择晶体管，而第一开关元件保持导通状态并且补偿两个位线之间的电位差。

4. 发明授权

US06538950B2 Integrated memory and corresponding operating method 有权
公开(公告)号：US06538950B2
公开(公告)日：2003-03-25
申请号：US09917553
申请日：2001-07-27
申请人： Thomas Böhm , Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Stefan Lammers , Thomas Rohr
发明人： Thomas Böhm , Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Stefan Lammers , Thomas Rohr
IPC分类号： G11C800
CPC分类号： G11C7/06 , G11C7/065 , G11C7/1006
摘要： An integrated memory has a multiplexer and a differential sense amplifier with a differential input. The differential sense amplifier is connected to three bit lines by the multiplexer. The multiplexer electrically connects the differential input of the sense amplifier to any two of the three bit lines connected to it respectively, in accordance with its activation.

5. 发明授权

US06480055B2 Decoder element for generating an output signal having three different potentials and an operating method for the decoder element 有权
标题翻译：用于产生具有三个不同电位的输出信号的解码器元件和用于解码器元件的操作方法
公开(公告)号：US06480055B2
公开(公告)日：2002-11-12
申请号：US09822028
申请日：2001-03-29
申请人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Ernst Neuhold , Thomas Röhr
发明人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Ernst Neuhold , Thomas Röhr
IPC分类号： H03K1776
CPC分类号： G11C5/143 , G11C8/08 , G11C16/12 , H03K19/09425 , H03M5/16
摘要： A decoder element is provided with an output, whereby an output signal with one of three different possible potentials is produced. The output signal may have a value of either a first potential, a second potential, and a third potential, where the second potential lies between the first potential and the third potential. The output signal is produced according to voltage values of input signals at terminal connections of the decoder element.
摘要翻译：解码器元件设置有输出，由此产生具有三种不同可能电位之一的输出信号。输出信号可以具有第一电位，第二电位和第三电位的值，其中第二电位位于第一电位和第三电位之间。输出信号根据解码器元件的端子连接处的输入信号的电压值而产生。

6. 发明授权

US06426640B1 Semiconductor module for burn-in test configuration 失效
标题翻译：半导体模块，用于老化测试配置
公开(公告)号：US06426640B1
公开(公告)日：2002-07-30
申请号：US09440803
申请日：1999-11-15
申请人： Norbert Wirth , Eric Cordes , Zoltan Manyoki , Dominique Savignac
发明人： Norbert Wirth , Eric Cordes , Zoltan Manyoki , Dominique Savignac
IPC分类号： G01R3102
CPC分类号： G01R31/2856 , G01R31/2884
摘要： The invention relates to a semiconductor module for a burn-in test configuration. The semiconductor module has a regulator which, when it is turned on, always supplies a constant low voltage to an internal circuit of the semiconductor module. The semiconductor module also contains a component which, when the burn-in voltage has been applied for a defined time period, supplies a different characteristic than when the internal voltage is applied.
摘要翻译：本发明涉及一种用于老化测试配置的半导体模块。半导体模块具有调节器，当其导通时，总是向半导体模块的内部电路提供恒定的低电压。半导体模块还包含当在已经施加了预定时间段的老化电压时提供与施加内部电压不同的特性的组件。

7. 发明授权

US6069486A Circuit configuration for reducing disturbances due to a switching of an output driver 有权
标题翻译：用于减少由于输出驱动器的切换引起的干扰的电路配置
公开(公告)号：US6069486A
公开(公告)日：2000-05-30
申请号：US160851
申请日：1998-09-25
申请人： Zoltan Manyoki , Christian Sichert , Ralf Schneider , Rainer Bartenschlager
发明人： Zoltan Manyoki , Christian Sichert , Ralf Schneider , Rainer Bartenschlager
IPC分类号： H03K17/12 , H03K17/16
CPC分类号： H03K17/162
摘要： A circuit configuration for reducing disturbances due to a switching of an output driver. The output driver has a plurality of output driver stages and a delay element. The delay element increases the signal delay of the switch-on or switch-off signals for the output driver stages with an increasing supply voltage.
摘要翻译：一种用于减少由于输出驱动器的切换引起的干扰的电路配置。输出驱动器具有多个输出驱动器级和延迟元件。延迟元件随着电源电压的增加而增加输出驱动器级的接通或关断信号的信号延迟。

8. 发明授权

US06392445B2 Decoder element for producing an output signal having three different potentials 失效
标题翻译：用于产生具有三个不同电位的输出信号的解码器元件
公开(公告)号：US06392445B2
公开(公告)日：2002-05-21
申请号：US09822027
申请日：2001-03-29
申请人： Thomas Röhr , Heinz Hönigschmid , Zoltan Manyoki , Thomas Böhm , Georg Braun , Ernst Neuhold
发明人： Thomas Röhr , Heinz Hönigschmid , Zoltan Manyoki , Thomas Böhm , Georg Braun , Ernst Neuhold
IPC分类号： G11C800
CPC分类号： H03M5/16
摘要： The decoder element is used for producing an output signal having three different potentials at an output. The second potential is situated between the first potential and the third potential. The decoder element makes it possible to produce any one of the three potentials at its output based upon the potentials on its connections.
摘要翻译：解码器元件用于在输出端产生具有三个不同电位的输出信号。第二电势位于第一电位和第三电位之间。解码器元件使得可以基于其连接上的电位在其输出端产生三个电位中的任何一个。

9. 发明授权

US06259641B1 Integrated memory having sense amplifiers disposed on opposite sides of a cell array 失效
标题翻译：具有设置在单元阵列的相对侧上的读出放大器的集成存储器
公开(公告)号：US06259641B1
公开(公告)日：2001-07-10
申请号：US09560545
申请日：2000-04-28
申请人： Zoltan Manyoki , Thomas Röhr , Thomas Böhm
发明人： Zoltan Manyoki , Thomas Röhr , Thomas Böhm
IPC分类号： G11C700
CPC分类号： G11C11/22 , G11C7/06 , G11C7/1042
摘要： An integrated memory includes a cell array having memory cells disposed at points of intersection of first bit lines and second bit lines with word lines in the cell array. When one of the memory cells is addressed, the memory content is not affected if respective bit lines associated with each of the memory cells are at a standby potential. Sense amplifiers for amplifying data read from the memory cells onto the bit lines are included, each associated with respective first and second bit lines and disposed on opposite sides of the cell array. Also provided are first switching elements, through which each bit line is connected to the associated sense amplifier, and second switching elements, through which each bit line is connected, on that side of its first switching element which is remote from the associated sense amplifier, to a standby potential. Column selection lines are each connected to the control connections of the first and second switching elements in at least one of the first and one of the second bit lines. Each bit line is connected to the standby potential through third switching elements. A first control line is connected to all the third switching elements in the first bit lines, and a second control line is connected to all the third switching elements in the second bit lines.
摘要翻译：集成存储器包括具有存储单元阵列的单元阵列，该存储单元设置在第一位线和第二位线的交点处与单元阵列中的字线。当存储器单元之一被寻址时，如果与每个存储器单元相关联的各个位线处于待机电位，则存储器内容不受影响。包括用于将从存储器单元读取的数据放大到位线的读出放大器，每个与相应的第一和第二位线相关联并且设置在单元阵列的相对侧上。还提供了第一开关元件，每个位线通过该开关元件连接到相关联的读出放大器，以及在其第一开关元件的远离相关读出放大器的该侧上连接每个位线的第二开关元件，到备用电位。列选择线各自连接到第一和第二位线中的至少一个中的第一和第二开关元件的控制连接。每个位线通过第三个开关元件连接到待机电位。第一控制线连接到第一位线中的所有第三开关元件，第二控制线连接到第二位线中的所有第三开关元件。

10. 发明授权

US06255855B1 Integrated circuit having a decoder 有权
标题翻译：具有解码器的集成电路
公开(公告)号：US06255855B1
公开(公告)日：2001-07-03
申请号：US09470310
申请日：1999-12-22
申请人： Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Thomas Röhr , Thomas Böhm
发明人： Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Thomas Röhr , Thomas Böhm
IPC分类号： H03K19084
CPC分类号： G11C8/00 , G11C8/10 , H03K19/084 , H03K19/094 , H03K19/23 , H03M5/16
摘要： An integrated circuit includes a decoder having an output terminal and five input terminals. The decoder has three operating states including a first operating state for generating a first potential at the output terminal, a second operating state for generating a second potential at the output terminal, and a third operating state for generating a third potential at the output terminal. The second potential lies between the first potential and the third potential.
摘要翻译：集成电路包括具有输出端和五个输入端的解码器。解码器具有三个操作状态，包括用于在输出端产生第一电位的第一操作状态，用于在输出端产生第二电位的第二操作状态和用于在输出端产生第三电位的第三操作状态。第二个潜力位于第一个潜力和第三个潜力之间。

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