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1. 发明授权

US4228520A High speed multiplier using carry-save/propagate pipeline with sparse carries 失效
标题翻译：高速乘法器采用携带保存/传播管道与稀疏携带
公开(公告)号：US4228520A
公开(公告)日：1980-10-14
申请号：US36198
申请日：1979-05-04
申请人： Robert C. Letteney , Samuel R. Levine , David T. Shen , Arnold Weinberger
发明人： Robert C. Letteney , Samuel R. Levine , David T. Shen , Arnold Weinberger
IPC分类号： G06F7/505 , G06F7/483 , G06F7/52 , G06F7/53 , G06F7/533 , G06F7/50
CPC分类号： G06F7/5334
摘要： A high speed multiply apparatus minimizes latch requirements and I/O pin requirement between chips by a new configuration which iteratively adds four multiples of a multiplicand in a stage of 4-2 carry save adders which then feed four-bit parallel adders each having four sum outputs and a carry output from the highest order bit position. Only the sum outputs are latched and then fed to a carry propagate adder on each iteration for addition to the previous partial products. Only the single carry output from each of the 4-bit parallel adders needs to be latched and then fed to another 4-bit parallel adder.
摘要翻译：高速乘法装置通过新的配置最小化锁存器要求和芯片之间的I / O引脚要求，该新配置在4-2级中迭代地添加被乘数的四个倍数，然后提供四位并行加法器，每个加法器具有四个和输出和最高位位置的进位输出。只有和输出被锁存，然后在每个迭代上馈送到进位传播加法器，以添加到先前的部分乘积。只需要从每个4位并行加法器的单个进位输出锁存，然后馈送到另一个4位并行加法器。

2. 发明授权

US4380813A Error checking of mutually-exclusive control signals 失效
标题翻译：错误检查互斥控制信号
公开(公告)号：US4380813A
公开(公告)日：1983-04-19
申请号：US249808
申请日：1981-04-01
申请人： Leonard L. Fogell , Samuel R. Levine , Arnold Weinberger
发明人： Leonard L. Fogell , Samuel R. Levine , Arnold Weinberger
IPC分类号： G06F11/00 , G06F11/08 , H03M13/51 , G06F11/12
CPC分类号： G06F11/085
摘要： This error checker determines if more than one set of control signals F1 through FN are on and also flags invalid as opposed to valid situations where none of the control signals F1 to FN are on. To distinguish the invalid from valid situations where none of the control signals F1 to FN are on, an additional control signal X=F1.multidot.F2.multidot. . . . .multidot.FN is generated and then fed with the control signals F1 to FN through a prior art detector which detects when more than one or none of the control signals X and F1 through FN are on.
摘要翻译：该错误检查器确定是否有多组控制信号F1至FN打开，并且标志无效，而不是控制信号F1至FN中没有一个的有效情况。为了将无效与不存在控制信号F1至FN的有效情况区分开，附加控制信号X = F1xF2x。的。的。产生xFN，然后通过现有技术的检测器馈送控制信号F1至FN，该检测器检测何时多于一个或者没有控制信号X和F1至FN导通。

3. 发明授权

US4118786A Integrated binary-BCD look-ahead adder 失效
标题翻译：集成二进制BCD预先加法器
公开(公告)号：US4118786A
公开(公告)日：1978-10-03
申请号：US758378
申请日：1977-01-10
申请人： Samuel R. Levine , Shanker Singh , Arnold Weinberger
发明人： Samuel R. Levine , Shanker Singh , Arnold Weinberger
IPC分类号： G06F7/493 , G06F7/494 , G06F7/50 , G06F7/508
CPC分类号： G06F7/494 , G06F7/508 , G06F2207/3844 , G06F2207/4921
摘要： An improved system for adding two numbers together. The numbers may be expressed either in binary form or in binary coded decimal form (wherein each decimal digit is represented by its equivalent four binary bits). By taking advantage of "don't care" decimal input conditions, a minimal implementation of a carry look-ahead adder which can operate upon both types of numbers is obtained.
摘要翻译：一个改进的系统，将两个数字加在一起。数字可以以二进制形式或二进制编码十进制形式表示（其中每个十进制数字由其等效的四个二进制位表示）。通过利用“无关”十进制输入条件，可以获得可以对两种类型的数字进行操作的进位预读加法器的最小实现。

4. 发明授权

US5365204A CMOS voltage controlled ring oscillator 失效
标题翻译： CMOS压控环形振荡器
公开(公告)号：US5365204A
公开(公告)日：1994-11-15
申请号：US145364
申请日：1993-10-29
申请人： John M. Angiulli , Arun K. Ghose , Richard R. Konian , Samuel R. Levine , David Meltzer , Wen-Yuan Wang , Leon L. Wu
发明人： John M. Angiulli , Arun K. Ghose , Richard R. Konian , Samuel R. Levine , David Meltzer , Wen-Yuan Wang , Leon L. Wu
IPC分类号： H03K3/03 , H03K3/354 , H03B5/24
CPC分类号： H03K3/354 , H03K3/0315
摘要： A variable frequency digital ring oscillator which can be formed in a small area for use in testing of chips employs a ring oscillator formed of CMOS inverters, transmission gates and capacitors and CMOS logic as a voltage controlled ring oscillator. A wide range of frequency of oscillation is achieved with small number of components. The ring oscillator circuit's oscillator frequency is controlled only by DC voltages, such as may be provided by (but not limited to) a manufacturing chip tester. The output signal of the oscillator swings between Vdd and Vss and does not need additional level translation circuits to drive CMOS logic. The ring oscillator can be composed of an odd number of CMOS inverters connected in cascade to form a loop. We provide a CMOS transmission gate with PMOS and NMOS transistor device inserted between each adjacent inverter and a MOS capacitor connected between the output of each transmission gate and the Vss supply of the ring oscillator circuit (conventionally ground). The gate voltages of the PMOS and NMOS transistors in the transmission gate are different and provide a different DC voltage between Vdd and Vss. Variation of the gate voltages of the transmission gates controls the frequency of oscillation of the circuit. The use of a plurality of cascaded delay elements between inverters achieves a wider range of oscillation frequency than possible with a single delay element.
摘要翻译：可以形成在用于芯片测试的小区域中的可变频数字环形振荡器采用由CMOS反相器，传输门和电容器形成的环形振荡器和作为压控环形振荡器的CMOS逻辑。通过少量组件实现了宽范围的振荡。环形振荡器电路的振荡器频率仅由直流电压控制，例如可以由（但不限于）制造芯片测试器提供。振荡器的输出信号在Vdd和Vss之间摆动，不需要额外的电平转换电路来驱动CMOS逻辑。环形振荡器可以由串联连接的奇数CMOS反相器组成，形成一个环路。我们提供一个CMOS传输门，PMOS和NMOS晶体管器件插在每个相邻的反相器和连接在每个传输门的输出和环形振荡器电路的Vss电源（传统接地）之间的MOS电容器。传输门中PMOS和NMOS晶体管的栅极电压不同，并在Vdd和Vss之间提供不同的直流电压。传输门的栅极电压的变化控制电路的振荡频率。在逆变器之间使用多个级联延迟元件实现比单个延迟元件可能的更宽的振荡频率范围。

5. 发明授权

US5323293A Arrangement for placing central processors and memory in a cryo cooled chamber 失效
标题翻译：将中央处理器和存储器放置在冷冻冷却室中的布置
公开(公告)号：US5323293A
公开(公告)日：1994-06-21
申请号：US993271
申请日：1992-12-18
申请人： John M. Angiulli , Arun K. Ghose , Richard R. Konian , Samuel R. Levine , Kevin P. Moran , Vincent C. Vasile
发明人： John M. Angiulli , Arun K. Ghose , Richard R. Konian , Samuel R. Levine , Kevin P. Moran , Vincent C. Vasile
IPC分类号： H05K7/20
CPC分类号： H05K7/20372
摘要： A low temperature conduction module comprising a cold plate having recesses around the periphery thereof to accommodate memory cubes is disclosed. The recesses accommodating the memory cubes are of such depth and dimension as to enclose the memory cube on all but one side, thereby greatly enhancing the conduction of the heat generated by the memory cube to the cold plate. The memory cube may be surrounded by a material which possesses excellent thermal conductive properties to insure efficient transfer of the heat from the memory cube to the cold plate. The plurality of memory cubes so positioned within the cold plate may be connected by a flexible cable surrounding the cold plate and having branch conductors extending to connect with computer processors enclosed within the same low temperature conduction module.
摘要翻译：公开了一种低温传导模块，其包括具有围绕其周边的凹部以容纳存储器立方体的冷板。容纳存储器立方体的凹部具有如此的深度和尺寸，以便将记忆立方体包围在除了一侧之外的所有记忆立方体上，从而大大增强了存储立方体产生的热传导到冷板。记忆立方体可以被具有优异导热性质的材料所围绕，以确保将热量从存储立方体有效地传递到冷板。如此定位在冷板内的多个存储器立方体可以通过围绕冷板的柔性电缆连接，并且具有延伸的分支导体以与封闭在同一低温传导模块内的计算机处理器连接。

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