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1. 发明授权

US4939102A Method of growing III-V semiconductor layers with high effective hole concentration 失效
标题翻译：生长具有高有效孔浓度的III-V半导体层的方法
公开(公告)号：US4939102A
公开(公告)日：1990-07-03
申请号：US297716
申请日：1989-01-17
申请人： Robert A. Hamm , Roger J. Malik , Morton B. Panish , John F. Walker
发明人： Robert A. Hamm , Roger J. Malik , Morton B. Panish , John F. Walker
IPC分类号： H01L21/205 , H01L21/203
CPC分类号： H01L21/02392 , H01L21/02395 , H01L21/02463 , H01L21/02543 , H01L21/02546 , H01L21/02579 , H01L21/02631 , Y10S148/002 , Y10S148/041 , Y10S148/056 , Y10S148/169 , Y10S438/915
摘要： 36 We have discovered the III-V semiconductor layers with previously unattainably high effective hole concentrations can be produced by molecular growth processes (e.g. MBE) if an amphoteric dopant such as Be is used and if, during the growth of the highly doped III-V layer, the substrate is maintained at a temperature T.sub.g that is substantially lower than customarily used. For instance, a InGaAs layer with effective hole concentration 1.0.times.10.sup.20 cm.sup.-3 was grown at T.sub.g =450.degree. C., and a GaAs layer with effective hole concentration of 1.0.times.10.sup.20 cm.sup.-3 was grown at T.sub.g of 475.degree. C. The heavily doped III-V layers can be of device grade and can usefully be part of electronic devices such as high speed bipolar transistors.

2. 发明授权

US4894526A Infrared-radiation detector device 失效
标题翻译：红外辐射检测装置
公开(公告)号：US4894526A
公开(公告)日：1990-01-16
申请号：US97567
申请日：1987-09-15
申请人： Clyde G. Bethea , Kwong-Kit Choi , Barry F. Levine , Roger J. Malik , John F. Walker
发明人： Clyde G. Bethea , Kwong-Kit Choi , Barry F. Levine , Roger J. Malik , John F. Walker
IPC分类号： G01J1/02 , H01L31/0264 , H01L31/0352 , H01L31/09 , H01L31/10 , H01L31/101
CPC分类号： B82Y20/00 , H01L31/035236 , H01L31/101
摘要： A narrow-bandwidth, high-speed infrared radiation detector is based on tunneling of photo-excited electrons out of quantum wells. Infrared radiation incident on a superlattice of doped quantum wells gives rise to intersubband resonance radiation which excites electrons from the ground state into an excited state. A photocurrent results from excited electrons tunneling out of quantum wells. Conveniently, Group III-V materials can be used in device manufacture. Preferably, quantum well potential barriers are shaped so as to facilitate resonant tunneling of photocurrents as compared with dark current. Preferred device operation is at elevated bias voltage, giving rise to enhancement of photocurrent by a quantum-well-avalanche effect.

3. 发明授权

US06894362B2 Method and apparatus for a self-aligned heterojunction bipolar transistor using dielectric assisted metal liftoff process 失效
标题翻译：使用介质辅助金属剥离工艺的自对准异质结双极晶体管的方法和装置
公开(公告)号：US06894362B2
公开(公告)日：2005-05-17
申请号：US10402714
申请日：2003-03-28
申请人： Roger J. Malik
发明人： Roger J. Malik
IPC分类号： H01L21/331 , H01L29/00
CPC分类号： H01L29/66318 , H01L2224/0401 , H01L2224/06102 , H01L2224/1403 , H01L2924/1305 , H01L2924/00
摘要： Disclosed is a manufacturing method to fabricate Heterojunction Bipolar Transistors (HBTs) that enables self-alignment of emitter and base metal contact layers with precise sub-micron spacing using a dielectric-assisted metal lift-off process. Such an HBT process relies on the formation of an “H-shaped” dielectric (i.e., Si3N4/SiO2) mask conformally deposited on top of the emitter contact metallization that is used to remove excess base metal through lift-off by a wet chemical HF-based etch. This HBT process also uses a thin selective etch-stop layer buried within the emitter layer to prevent wet chemical over-etching to the base and improves HBT reliability by forming a non-conducting, depleted ledge above the extrinsic base layer. The geometry of the self-aligned emitter and base metal contacts in the HBT insures conformal coverage of dielectric encapsulation films, preferably Si3N4 and/or SiO2, for reliable HBT emitter p-n junction passivation. Thus, the disclosed HBT process enables scaling of narrow emitter stripe widths down to sub-micron dimensions producing transistors with cut-off frequencies in the range of several hundred GigaHertz.
摘要翻译：公开了一种制造异质结双极晶体管（HBT）的制造方法，其使用介电辅助金属剥离工艺使得发射极和母材接触层能够以精确的亚微米间距自对准。这种HBT工艺依赖于形成“H形”电介质（即，Si 3 N 4 N 2 O 3 / SiO 2）掩模沉积在用于通过湿化学HF基蚀刻通过剥离去除多余的基体金属的发射极接触金属化的顶部。该HBT工艺还使用掩埋在发射极层内的薄的选择性蚀刻停止层，以防止对基底的湿化学过度蚀刻，并通过在外部基极层之上形成非导电的耗尽凸缘来提高HBT的可靠性。 HBT中的自对准发射极和母体金属触点的几何形状确保电介质封装膜的适形覆盖，优选Si 3 N 4 N 2和/或SiO 2 ，用于可靠的HBT发射极pn结钝化。因此，所公开的HBT工艺能够将窄发射极条宽度缩小到亚微米尺寸，从而产生截止频率在几百千兆赫兹范围内的晶体管。

4. 发明授权

US4945393A Floating gate memory circuit and apparatus 失效
标题翻译：浮栅存储电路及装置
公开(公告)号：US4945393A
公开(公告)日：1990-07-31
申请号：US447286
申请日：1989-12-07
申请人： Fabio Beltram , Federico Capasso , Roger J. Malik , Nitin J. Shah
发明人： Fabio Beltram , Federico Capasso , Roger J. Malik , Nitin J. Shah
IPC分类号： G11C16/04 , H01L29/80
CPC分类号： G11C16/0433 , H01L29/803
摘要： A floating gate memory device comprises a channel for conducting carriers from source to drain, a semiconductor heterostructure forming a potential well (floating gate) for confining carriers sufficiently proximate the channel so as to at least partially deplete it, and a graded bandgap injector region between the control gate and the floating gate for controlling the injection of carriers into and out of the potential well. Also described is a three element memory cell, including the memory device and two FETs, which operates from a constant, non-switched supply voltage and two-level control voltages. Arrays of memory devices may also be used to detect light in a variety of applications such as imaging.
摘要翻译：浮动栅极存储器件包括用于从源极到漏极传导载流子的沟道，形成势阱（浮栅）的半导体异质结构，用于使载流子足够接近通道以使其至少部分耗尽;以及梯度带隙注入器区域，控制栅极和浮动栅极，用于控制载流子进入和离开潜在井的注入。还描述了一种三元件存储单元，其包括存储器件和两个FET，其从恒定的非开关电源电压和两电平控制电压工作。存储器件的阵列也可用于检测诸如成像的各种应用中的光。

5. 发明授权

US4905063A Floating gate memories 失效
标题翻译：浮动门记忆
公开(公告)号：US4905063A
公开(公告)日：1990-02-27
申请号：US209466
申请日：1988-06-21
申请人： Fabio Beltram , Federico Capasso , Roger J. Malik , Nitin J. Shah
发明人： Fabio Beltram , Federico Capasso , Roger J. Malik , Nitin J. Shah
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/80
CPC分类号： G11C16/0433 , H01L29/803 , Y10S257/903
摘要： A floating gate memory device comprises a channel for conducting carriers from source to drain, a semiconductor heterostructure forming a potential well (floating gate) for confining carriers sufficiently proximate the channel so as to at least partially deplete it, and a graded bandgap injector region between the control gate and the floating gate for controlling the injection of carriers into and out of the potential well. Also described is a three element memory cell, including the memory device and two FETs, which operates from a constant, non-switched supply voltage and two-level control voltages. Arrays of memory devices may also be used to detect light in a variety of applications such as imaging.

6. 发明授权

US06541346B2 Method and apparatus for a self-aligned heterojunction bipolar transistor using dielectric assisted metal liftoff process 失效
公开(公告)号：US06541346B2
公开(公告)日：2003-04-01
申请号：US09813293
申请日：2001-03-20
申请人： Roger J. Malik
发明人： Roger J. Malik
IPC分类号： H01L21331
CPC分类号： H01L29/66318 , H01L2224/0401 , H01L2224/06102 , H01L2224/1403 , H01L2924/1305 , H01L2924/00
摘要： Disclosed is a manufacturing method to fabricate Heterojunction Bipolar Transistors (HBTs) that enables self-alignment of emitter and base metal contact layers with precise sub-micron spacing using a dielectric-assisted metal lift-off process. Such an HBT process relies on the formation of an “H-shaped” dielectric (i.e., Si3N4/SiO2) mask conformally deposited on top of the emitter contact metalization that is used to remove excess base metal through lift-off by a wet chemical HF-based etch. This HBT process also uses a thin selective etch-stop layer buried within the emitter layer to prevent wet chemical over-etching to the base and improves HBT reliability by forming a non-conducting, depleted ledge above the extrinsic base layer. The geometry of the self-aligned emitter and base metal contacts in the HBT insures conformal coverage of dielectric encapsulation films, preferably Si3N4 and/or SiO2, for reliable HBT emitter p-n junction passivation. Thus, the disclosed HBT process enables scaling of narrow emitter stripe widths down to sub-micron dimensions producing transistors with cut-off frequencies in the range of several hundred GigaHertz.

7. 发明授权

US4247358A Method of growing single crystals of alpha aluminum phosphate 失效
标题翻译：生长α磷酸铝单晶的方法
公开(公告)号：US4247358A
公开(公告)日：1981-01-27
申请号：US46961
申请日：1979-06-08
申请人： Thomas R. AuCoin , Abraham Schwartz , Melvin J. Wade , Roger J. Malik
发明人： Thomas R. AuCoin , Abraham Schwartz , Melvin J. Wade , Roger J. Malik
IPC分类号： C30B7/00 , C30B7/10
CPC分类号： C30B7/00 , C30B29/14
摘要： Single crystals of alpha aluminum phosphate of high crystal perfection arerown from seeded solutions of aluminum orthophosphate and orthophosphoric acid in such a manner as to provide direct visual observation of the crystal growth process and allow precise determination of nucleation and growth kinetics.The method involves sealing the seeded solution in clear quartz ampules, inserting the ampules into a precisely temperature controlled silicone oil bath, increasing the temperature of the silicone oil bath from ambient temperature to approximately 150 degrees C. over a three hour period, programming the temperature of the bath upward at the rate of 0.1 to 2.0 degrees C. per day for periods up to sixty days, and removing the quartz ampules from the silicone oil bath and quickly cooling and removing the crystals.
摘要翻译：从正磷酸铝和正磷酸的接种溶液中生长出高结晶完整性的α磷酸铝单晶，以提供对晶体生长过程的直接目视观察，并允许精确测定成核和生长动力学。该方法包括将接种的溶液密封在透明的石英安瓿中，将安瓿插入精确温度控制的硅油浴中，在3小时内将硅油浴的温度从环境温度升高至约150℃，以0.1至2.0摄氏度的速率向上加热至60天，并从硅油浴中除去石英安瓿并快速冷却并除去晶体。

8. 发明申请

US20110297215A1 Manufacturing method and apparatus for a copper indium gallium diselenide solar cell 审中-公开
标题翻译：铜铟镓二硒化物太阳能电池的制造方法和装置
公开(公告)号：US20110297215A1
公开(公告)日：2011-12-08
申请号：US12802397
申请日：2010-06-04
申请人： Roger J. Malik
发明人： Roger J. Malik
IPC分类号： H01L31/0264 , H01L21/06
CPC分类号： H01L31/0322 , H01L21/02568 , H01L21/02579 , H01L21/02664 , H01L31/0323 , H01L31/068 , Y02E10/541 , Y02E10/547 , Y02P70/521
摘要： A method to manufacture Copper Indium Gallium di Selenide (Cu(In,Ga)Se2) thin film solar cell includes evaporating elemental Cu, In, Ga, and Se flux sources onto a heated substrate in a single vacuum system to form a non-intentionally doped Cu(In,Ga)Se2 p-type conductivity layer and exposing the p-type conductivity layer to a thermally evaporated flux of Beryllium (Be) atoms to convert a surface layer of the p-type conductivity layer to an n-type conductivity layer resulting in a buried Cu(In,Ga)Se2 p-n homojunction. Also, the source of Be atoms includes a circular rod of Be having a uniform cross-section that is resistively heated and having its temperature controlled by passing an electrical current through the rod.
摘要翻译：制造铜铟镓硒（Cu（In，Ga）Se2）薄膜太阳能电池的方法包括在单个真空系统中将元素Cu，In，Ga和Se元素蒸发到加热的衬底上以形成非故意的掺杂的Cu（In，Ga）Se2 p型导电层，并将p型导电层暴露于热蒸发的铍（Be）原子，以将p型导电层的表面层转变为n型导电性层导致埋入的Cu（In，Ga）Se2 pn同型结。此外，Be原子的源包括具有均匀横截面的Be的圆形棒，其被电阻加热并且通过使电流通过杆来控制其温度。

9. 发明授权

US4563773A Monolithic planar doped barrier subharmonic mixer 失效
标题翻译：单片平面掺杂阻挡次谐波混频器
公开(公告)号：US4563773A
公开(公告)日：1986-01-07
申请号：US588612
申请日：1984-03-12
申请人： Samuel Dixon, Jr. , Roger J. Malik
发明人： Samuel Dixon, Jr. , Roger J. Malik
IPC分类号： H03D9/06 , H04B1/26
CPC分类号： H03D9/0641 , H03D2200/0017
摘要： A single planar doped barrier diode is grown by the selective deposition of gallium arsenide using molecular beam epitaxy (MBE) in the center of a gallium arsenide dielectric waveguide member mounted on a ground plane. The waveguide member includes two portions which extend in opposite directions and terminating in respective metal to dielectric waveguide transition sections which are coupled to an RF input signal and local oscillator signal, respectively. The planar doped barrier diode operates as an intrinsic subharmonic mixer and accordingly the local oscillator signal has frequency of one half the input signal frequency. An IF output signal is coupled from the mixer diode to a microstrip transmission line formed on an insulating layer fabricated on the ground plane. Dielectric waveguide isolators are additionally included on the dielectric waveguide segments to mutually isolate the input signal and local oscillator signal. A monolithic form of circuit fabrication is thus provided which allows the planar doped barrier mixer circuit to be extremely small and the cost of mass producing such a circuit to be very economical.
摘要翻译：通过使用分子束外延（MBE）在安装在接地平面上的砷化镓电介质波导部件的中心选择性沉积砷化镓来生长单个平面掺杂势垒二极管。波导构件包括两个部分，这两个部分在相反的方向上延伸并终止于分别与RF输入信号和本地振荡器信号耦合的电介质波导过渡部分的相应金属。平面掺杂势垒二极管作为内部次谐波混频器工作，因此本地振荡器信号具有输入信号频率的一半的频率。 IF输出信号从混频器二极管耦合到形成在制造在接地平面上的绝缘层上的微带传输线。电介质波导隔离器还包括在电介质波导段上，以相互隔离输入信号和本地振荡器信号。因此，提供了一种单片形式的电路制造，其允许平面掺杂阻挡混合器电路非常小，并且大量生产这种电路的成本非常经济。

10. 发明授权

US4539581A Planar doped barrier transferred electron oscillator 失效
标题翻译：平面掺杂势垒转移电子振荡器
公开(公告)号：US4539581A
公开(公告)日：1985-09-03
申请号：US397340
申请日：1982-07-12
申请人： Roger J. Malik , Gerald J. Iafrate
发明人： Roger J. Malik , Gerald J. Iafrate
IPC分类号： H01L47/02 , H01L27/26 , H01L29/12
CPC分类号： H01L47/026
摘要： A transferred electron semiconductor device in the form of an oscillator, for example, is fabricated by a molecular beam epitaxy growth process wherein a plurality of semiconductor layers are sequentially grown on a planar substrate. A pair of ohmic contacts are formed on the outer surface of the substrate and the uppermost layer with the resulting structure including two distinct intermediate semiconductor regions, the first being a drift region adapted to exhibit a differential negative resistance due to the transferred electron effect, and the second being a planar doped barrier region for accelerating electrons into the upper valley and injecting them into the drift region. By the use of a planar doped barrier a more uniform electric field is obtained along with a controlled lower barrier height whereby the transfer of electrons to the upper conduction band satellite valley can be made to occur over much shorter times and distances thus extending the upper frequency range of operation.
摘要翻译：例如通过分子束外延生长工艺制造振荡器形式的转移电子半导体器件，其中多个半导体层在平面衬底上顺序生长。在基板的外表面和最上层形成一对欧姆接触，所得到的结构包括两个不同的中间半导体区域，第一个是由于转移的电子效应而表现出差分负电阻的漂移区域，以及第二个是用于将电子加速到上部谷中并将它们注入到漂移区域中的平面掺杂阻挡区域。通过使用平面掺杂阻挡层，获得更均匀的电场以及受控的较低势垒高度，由此可以使电子向上导带卫星谷的转移发生在更短的时间和距离上，从而延长上部频率操作范围。

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