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1. 发明公开

CN102099913A 纳米结构存储器件无效
公开(公告)号：CN102099913A
公开(公告)日：2011-06-15
申请号：CN200980126703.6
申请日：2009-07-02
申请人：昆南诺股份有限公司
发明人： L·萨穆尔森 , C·塞兰德 , J·奥尔森 , A·米克尔森
IPC分类号： H01L27/105 , H01L29/02 , H01L29/06 , H01L29/12 , H01L29/80
CPC分类号： H01L29/7881 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/42332 , H01L29/66825 , H01L29/803 , Y10S977/938
摘要：本发明提供一种纳米结构存储器件，其包括形成电流输送沟道的至少一半导体纳米线(3)，设置在该纳米线(3)的至少一部分周围的一个或多个壳层(4)，和嵌入到所述一个或多个壳层(4)的纳米尺寸电荷俘获中心(10)，以及至少设置在所述一个或多个壳层(4)的相应部分的一个或多个栅电极(14)。优选地，所述一个或多个壳层(4)由宽带隙材料或绝缘体制成。通过使用所述一个或多个栅电极(14)，该电荷俘获中心(10)可被充电/写入，并且存储在电荷俘获中心(10)的一个或多个中的电荷量的变化改变纳米线(3)的导电性。

2. 发明申请

WO2007016477A2 NORMALLY OFF III-NITRIDE SEMICONDUCTOR DEVICE HAVING A PROGRAMMABLE GATE 审中-公开
标题翻译：正常关闭具有可编程门的III-NITRIDE半导体器件
公开(公告)号：WO2007016477A2
公开(公告)日：2007-02-08
申请号：PCT/US2006029709
申请日：2006-07-31
申请人： INT RECTIFIER CORP , BRIERE MICHAEL A
发明人： BRIERE MICHAEL A
IPC分类号： H01L21/84
CPC分类号： H01L29/778 , H01L29/2003 , H01L29/4232 , H01L29/42328 , H01L29/42336 , H01L29/51 , H01L29/513 , H01L29/518 , H01L29/66431 , H01L29/772 , H01L29/7787 , H01L29/803
摘要： A III-nitride semiconductor device which includes a charged gate insulation body.
摘要翻译：一种III族氮化物半导体器件，包括带电栅极绝缘体。

3. 发明申请

WO1991013465A1 ELECTRONIC DEVICES AND METHODS OF CONSTRUCTING AND UTILIZING SAME 审中-公开
标题翻译：电子设备及其构造和使用方法
公开(公告)号：WO1991013465A1
公开(公告)日：1991-09-05
申请号：PCT/US1991001146
申请日：1991-02-22
申请人： SYMETRIX CORPORATION
发明人： SYMETRIX CORPORATION , PAZ DE ARAUJO, Carlos, A. , MCMILLIAN, Larry, D.
IPC分类号： H01L29/78
CPC分类号： H01L29/513 , H01L27/11502 , H01L29/475 , H01L29/516 , H01L29/517 , H01L29/518 , H01L29/739 , H01L29/7391 , H01L29/803 , H01L29/808
摘要： A device (1) having a semiconductor junction whose electrical charge volume is controlled by a ferroelectric element (5). The ferroelectric (5) establishes the level of leakage of the pn junction to provide a gate-controlled diode or transistor device. The bipolar three-terminal gated diode may be used in memory matrices, neural synaptic networks, DRAM units, bipolar transistors, JFETs, and gallium arsenide and AlGaAs heterostructures.
摘要翻译：一种具有半导体结的器件（1），其电荷量由铁电元件（5）控制。铁电体（5）建立了pn结的泄漏电平，以提供栅极控制二极管或晶体管器件。双极三端门控二极管可用于存储器矩阵，神经突触网络，DRAM单元，双极晶体管，JFET以及砷化镓和AlGaAs异质结构。

4. 发明申请

WO2012136206A3 MEMORY CELL 审中-公开
标题翻译： CELL
公开(公告)号：WO2012136206A3
公开(公告)日：2012-12-13
申请号：PCT/DE2012200019
申请日：2012-03-29
申请人： UNIV BERLIN TECH , MARENT ANDREAS , BIMBERG DIETER
发明人： MARENT ANDREAS , BIMBERG DIETER
IPC分类号： H01L29/80 , B82Y10/00 , G11C16/04 , H01L29/788
CPC分类号： G11C16/0466 , B82Y10/00 , G11C16/0408 , G11C16/14 , G11C16/26 , H01L29/788 , H01L29/803
摘要： The invention relates to a memory cell (10) comprising at least one binary memory area for storing an item of bit information and to a method for storing an item of bit information. According to the invention, it is provided that the memory area (SB), e.g. a quantum dot layer of In(Ga)As quantum dots, can optionally store holes or electrons and allows a recombination of holes and electrons, the charge carrier type of the charge carriers stored in the memory area defines the bit information of the memory area and a charge carrier injection device (PN) is present, by means of which optionally holes or electrons can be injected into the memory area (SB) and the bit information can thus be changed. The holes and electrons come from a hole reservoir (LR) or electron reservoir (ER) which consist e.g. of p-doped or n-doped GaAs. The readout layer (AS) is a two-dimensional hole or electron gas layer.
摘要翻译：本发明涉及一种具有用于存储位信息的至少一个二进制存储区域的存储单元（10），以及用于存储Bitinfomation的方法。根据本发明，它提供的是，存储器区域（SB），例如。例如，在量子点层（Ga）的量子点，wahl¬例如可以存储空穴或电子和空穴和电子的重组允许存储在载流子的存储区域中的数据的电荷载流子确定的存储器区域的所述位信息，并提供一个电荷载流子注入装置（PN）是，与可选的空穴或电子到存储器区域（SB）可以被注入，从而将位可被改变。空穴和电子从空穴（LR）或电子储存器（ER），其例如源于由p型或n型掺杂的GaAs构成。读出层（AS）是一二维空穴或电子气层。

5. 发明公开

EP0202755A1 Double heterojunction field effect transistor data storage device 失效
标题翻译：电子邮件Doppelheteroübergangs-Feldeffekttramistor bestehendes Datenspeicherelement。
公开(公告)号：EP0202755A1
公开(公告)日：1986-11-26
申请号：EP86302730.6
申请日：1986-04-11
申请人： International Business Machines Corporation
发明人： Freeouf, John Lawrence , Jackson, Thomas Nelson , Kirchner, Peter Daniel
IPC分类号： H01L29/80 , H01L29/64
CPC分类号： H01L29/205 , H01L29/778 , H01L29/803
摘要： Reversible control of conduction in a band offset heterojunction field effect transistor device is achieved by .an asymmetric barrier (10) which can position a potential well across the Fermi level to produce conduction and away from the Fermi level for a non-conducting condition and to retain that position in the absence of a signal. The device can be a GaAs channel FET with a multilayer gate comprising, in order of proximity to the GaAs channel, a gate layer (3) of GaA1As, a charge storage layer (8) of GaAs, an asymmetric barrier layer (10) of GaA1As graded towards the GaAs storage layer and an ohmic adapting layer (13) of GaAs.
摘要翻译：带偏移异质结场效应晶体管器件中的导通的可逆控制是通过非对称势垒（10）来实现的，该不对称势垒（10）可将势阱定位在费米能级上以产生导通并远离费米能级用于非导通状态并保持那个位置在没有信号的情况下。所述器件可以是具有多层栅极的GaAs沟道FET，所述GaAs沟道FET包括依次接近GaAs沟道的GaAlAs的栅极层（3），GaAs的电荷存储层（8），不对称势垒层（10）， GaAlAs分级到GaAs存储层和GaAs的欧姆适配层（13）。

6. 发明公开

EP0165433A2 High-speed field-effect transistor 失效
标题翻译：高速场效应晶体管。
公开(公告)号：EP0165433A2
公开(公告)日：1985-12-27
申请号：EP85105648.1
申请日：1985-05-08
申请人： HITACHI, LTD.
发明人： Umemoto, Yasunari , Takahashi, Susumu , Ono, Yuichi
IPC分类号： H01L29/76 , H01L29/64
CPC分类号： H01L29/4916 , H01L29/432 , H01L29/4966 , H01L29/802 , H01L29/803 , Y10S148/053 , Y10S148/072 , Y10S148/088 , Y10S148/097
摘要： Herein disclosed is a semiconductor device in which control means for carriers migrating in a first semiconductor (11) includes an interface state layer (12) lying on the first semiconductor (11) and a second conductor layer (13) lying on the interface state layer (12). The interface state layer (12) has its Fermi level pinned to that of the second semiconductor layer (13). By thus constructing an FET or the semiconductor device, an inversion or storage layer can be easily formed in the interface merely by applying a voltage to the control means.

7. 发明授权

US08729644B2 Programmable III-nitride semiconductor device 有权
标题翻译：可编程III族氮化物半导体器件
公开(公告)号：US08729644B2
公开(公告)日：2014-05-20
申请号：US13906098
申请日：2013-05-30
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L21/02
CPC分类号： H01L29/778 , H01L29/2003 , H01L29/4232 , H01L29/42328 , H01L29/42336 , H01L29/51 , H01L29/513 , H01L29/518 , H01L29/66431 , H01L29/772 , H01L29/7787 , H01L29/803
摘要： A III-nitride semiconductor device which includes a charged gate insulation body.
摘要翻译：一种III族氮化物半导体器件，包括带电栅极绝缘体。

8. 发明授权

US08482035B2 Enhancement mode III-nitride transistors with single gate Dielectric structure 有权
标题翻译：具有单栅极电介质结构的增强型III族氮化物晶体管
公开(公告)号：US08482035B2
公开(公告)日：2013-07-09
申请号：US13017970
申请日：2011-01-31
申请人： Michael A. Briere
发明人： Michael A. Briere
IPC分类号： H01L21/8232 , H01L29/778
CPC分类号： H01L29/7783 , H01L21/02063 , H01L21/76814 , H01L29/2003 , H01L29/205 , H01L29/4232 , H01L29/51 , H01L29/518 , H01L29/66431 , H01L29/66462 , H01L29/778 , H01L29/7787 , H01L29/803
摘要： According to one embodiment, a III-nitride transistor includes a conduction channel formed between first and second III-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel. The transistor can be an enhancement mode transistor. In one embodiment, the gate dielectric layer is a silicon nitride layer. In another embodiment, the at least one gate dielectric layer is a silicon oxide layer. The charge can be ion implanted into the at least one gate dielectric layer. The at least one gate dielectric layer can also be grown with the charge.
摘要翻译：根据一个实施例，III族氮化物晶体管包括在第一和第二III族氮化物体之间形成的导电通道，该导电通道包括二维电子气。所述晶体管还包括至少一个具有限制在其中的电荷的栅介质层，以引起导通通道的中断区域，以及可操作以恢复导通通道的中断区域的栅电极。晶体管可以是增强型晶体管。在一个实施例中，栅介质层是氮化硅层。在另一个实施例中，至少一个栅介质层是氧化硅层。电荷可以离子注入到至少一个栅极电介质层中。至少一个栅介电层也可以与电荷一起生长。

9. 发明授权

US08331142B2 Memory 有权
标题翻译：记忆
公开(公告)号：US08331142B2
公开(公告)日：2012-12-11
申请号：US12970744
申请日：2010-12-16
申请人： Dieter Bimberg , Martin Geller , Andreas Marent , Tobias Nowozin
发明人： Dieter Bimberg , Martin Geller , Andreas Marent , Tobias Nowozin
IPC分类号： G11C11/34 , H01L29/68
CPC分类号： B82Y10/00 , H01L29/66825 , H01L29/788 , H01L29/803
摘要： An embodiment of the invention relates to a memory comprising a strained double-heterostructure having an inner semiconductor layer which is sandwiched between two outer semiconductor layers, wherein the lattice constant of the inner semiconductor layer differs from the lattice constants of the outer semiconductor layers, the resulting lattice strain in the double-heterostructure inducing the formation of at least one quantum dot inside the inner semiconductor layer, said at least one quantum dot being capable of storing charge carriers therein, and wherein, due to the lattice strain, the at least one quantum dot has an emission barrier of 1.15 eV or higher, and provides an energy state density of at least three energy states per 1000 nm3, all said at least three energy states being located in an energy band of 50 meV or less.
摘要翻译：本发明的一个实施例涉及包含应变双异质结构的存储器，其具有夹在两个外半导体层之间的内半导体层，其中内半导体层的晶格常数与外半导体层的晶格常数不同，所述双异质结构中的晶格应变导致在所述内半导体层内部形成至少一个量子点，所述至少一个量子点能够在其中存储电荷载流子，并且其中由于晶格应变，所述至少一个量子点具有1.15eV或更高的发射势垒，并且提供每1000nm 3至少三个能量状态的能态状态密度，所有所述至少三个能态位于50meV或更小的能带内。

10. 发明申请

US20120091470A1 Programmable Gate III-Nitride Power Transistor 有权
标题翻译：可编程门III-氮化物功率晶体管
公开(公告)号：US20120091470A1
公开(公告)日：2012-04-19
申请号：US13334720
申请日：2011-12-22
申请人： Michael A. Briere
发明人： Michael A. Briere
IPC分类号： H01L29/161 , H01L21/20 , H01L29/20
CPC分类号： H01L29/778 , H01L29/2003 , H01L29/4232 , H01L29/42328 , H01L29/42336 , H01L29/51 , H01L29/513 , H01L29/518 , H01L29/66431 , H01L29/772 , H01L29/7787 , H01L29/803
摘要： A III-nitride semiconductor device which includes a charged floating gate electrode.
摘要翻译：一种III族氮化物半导体器件，其包括带电的浮置栅电极。

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