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1. 发明授权

US06538945B2 Sense amplifiers having reduced Vth deviation 有权
公开(公告)号：US06538945B2
公开(公告)日：2003-03-25
申请号：US10050561
申请日：2002-01-18
申请人： Riichiro Takemura , Tsugio Takahashi , Masayuki Nakamura , Ryo Nagai , Norikatsu Takaura , Tomonori Sekiguchi , Shinichiro Kimura
发明人： Riichiro Takemura , Tsugio Takahashi , Masayuki Nakamura , Ryo Nagai , Norikatsu Takaura , Tomonori Sekiguchi , Shinichiro Kimura
IPC分类号： G11C700
CPC分类号： G11C7/065 , G11C11/4091 , H01L21/823807 , H01L27/092 , H01L27/10873 , H01L27/10897
摘要： Providing a semiconductor device which lessen influence of the transistor threshold voltage deviation that is one of noise elements when the sense amplifiers are amplified, and which are capable of accurately sensing and amplifying micro signals having read from the memory cells in the sense amplifiers. In a DRAM chip, P+-type gate PMOSs of P+-type polysilicon gates each having a low impurity density of channel and N+-type gate NMOSs of N+-type polysilicon gates are used in a sense amplifier cross coupling section to further increase substrate voltages of the PMOSs and to decrease substrate voltages of the NMOS. For this reason, a deviation of threshold voltage caused by channel implantation is reduced, and a small signal generated on a data line at a read operation of a low-potential memory array is accurately sensed and amplified by a sense amplifier. In addition, the threshold voltages are increased by a substrate bias effect, and a leakage current in a sense amplifier data holding state is reduced.

2. 发明申请

US20050035428A1 Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路器件
公开(公告)号：US20050035428A1
公开(公告)日：2005-02-17
申请号：US10946000
申请日：2004-09-22
申请人： Norikatsu Takaura , Riichiro Takemura , Hideyuki Matsuoka , Shinichiro Kimura , Hisao Asakura , Ryo Nagai , Satoru Yamada
发明人： Norikatsu Takaura , Riichiro Takemura , Hideyuki Matsuoka , Shinichiro Kimura , Hisao Asakura , Ryo Nagai , Satoru Yamada
IPC分类号： H01L21/76 , H01L21/8238 , H01L21/8242 , H01L27/08 , H01L27/092 , H01L27/105 , H01L27/108 , H01L29/76
CPC分类号： H01L27/105 , H01L27/10897
摘要： A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4-L5), (L6-L5), and (L4-L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.
摘要翻译：提供了一种半导体集成电路器件，其中可以减小MISFET的阈值电压的变化，例如构成读出放大器的MISFET对的变化。在形成驱动存储单元所需的诸如读出放大器电路的逻辑电路的逻辑电路区域中，没有栅电极的n型有源区域被布置在有效区域的两个边缘上，p沟道MISFET对用于构成读出放大器。假设有效区域nwp1和nw1之间的宽度为L4，则有效区域nwp2和nw2之间的宽度为L6，有效区域nwp1和nwp2之间的宽度为L5（L4-L5），（L6-L5）和（ L4-L6）设定为几乎为零或小于最小加工尺寸的两倍，使得可以减小宽度L4，L5和L6的器件隔离沟槽形状的变化，并且可以减小阈值电压差可以减少MISFET对。

3. 发明授权

US06812540B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06812540B2
公开(公告)日：2004-11-02
申请号：US10298682
申请日：2002-11-19
申请人： Norikatsu Takaura , Riichiro Takemura , Hideyuki Matsuoka , Shinichiro Kimura , Hisao Asakura , Ryo Nagai , Satoru Yamada
发明人： Norikatsu Takaura , Riichiro Takemura , Hideyuki Matsuoka , Shinichiro Kimura , Hisao Asakura , Ryo Nagai , Satoru Yamada
IPC分类号： H01L2900
CPC分类号： H01L27/105 , H01L27/10897
摘要： A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4−L5), (L6−L5), and (L4−L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.
摘要翻译：提供了一种半导体集成电路器件，其中可以减小MISFET的阈值电压的变化，例如构成读出放大器的MISFET对的变化。在形成驱动存储单元所需的诸如读出放大器电路的逻辑电路的逻辑电路区域中，没有栅电极的n型有源区域被布置在有效区域的两个边缘上，p沟道MISFET对用于构成读出放大器。假设有源区域nwp1和nw1之间的宽度为L4，有效区域nwp2和nw2之间的宽度为L6，有效区域nwp1和nwp2之间的宽度为L5（L4-L5），（L6-L5）和（ L4-L6）设定为几乎为零或小于最小加工尺寸的两倍，使得可以减小宽度L4，L5和L6的器件隔离沟槽形状的变化，并且可以减小阈值电压差可以减少MISFET对。

4. 发明授权

US07098478B2 Semiconductor memory device using vertical-channel transistors 失效
公开(公告)号：US07098478B2
公开(公告)日：2006-08-29
申请号：US11168872
申请日：2005-06-29
申请人： Norikatsu Takaura , Hideyuki Matsuoka , Riichiro Takemura , Kousuke Okuyama , Masahiro Moniwa , Akio Nishida , Kota Funayama , Tomonori Sekiguchi
发明人： Norikatsu Takaura , Hideyuki Matsuoka , Riichiro Takemura , Kousuke Okuyama , Masahiro Moniwa , Akio Nishida , Kota Funayama , Tomonori Sekiguchi
IPC分类号： H01L29/72
CPC分类号： H01L27/11 , H01L27/0688 , H01L27/1104
摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

5. 发明授权

US06670642B2 Semiconductor memory device using vertical-channel transistors 失效
公开(公告)号：US06670642B2
公开(公告)日：2003-12-30
申请号：US10051188
申请日：2002-01-22
申请人： Norikatsu Takaura , Hideyuki Matsuoka , Riichiro Takemura , Kousuke Okuyama , Masahiro Moniwa , Akio Nishida , Kota Funayama , Tomonori Sekiguchi
发明人： Norikatsu Takaura , Hideyuki Matsuoka , Riichiro Takemura , Kousuke Okuyama , Masahiro Moniwa , Akio Nishida , Kota Funayama , Tomonori Sekiguchi
IPC分类号： H01L2972
CPC分类号： H01L27/11 , H01L27/0688 , H01L27/1104
摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

6. 发明授权

US06943373B2 Semiconductor memory device using vertical-channel transistors 失效
公开(公告)号：US06943373B2
公开(公告)日：2005-09-13
申请号：US10693987
申请日：2003-10-28
申请人： Norikatsu Takaura , Hideyuki Matsuoka , Riichiro Takemura , Kousuke Okuyama , Masahiro Moniwa , Akio Nishida , Kota Funayama , Tomonori Sekiguchi
发明人： Norikatsu Takaura , Hideyuki Matsuoka , Riichiro Takemura , Kousuke Okuyama , Masahiro Moniwa , Akio Nishida , Kota Funayama , Tomonori Sekiguchi
IPC分类号： G11C11/41 , H01L21/8234 , H01L21/8244 , H01L27/00 , H01L27/06 , H01L27/088 , H01L27/10 , H01L27/11 , H01L29/10 , H01L29/72
CPC分类号： H01L27/11 , H01L27/0688 , H01L27/1104
摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

7. 发明申请

US20050253143A1 Semiconductor memory device using vertical-channel transistors 失效
标题翻译：半导体存储器件采用垂直沟道晶体管
公开(公告)号：US20050253143A1
公开(公告)日：2005-11-17
申请号：US11168872
申请日：2005-06-29
申请人： Norikatsu Takaura , Hideyuki Matsuoka , Riichiro Takemura , Kousuke Okuyama , Masahiro Moniwa , Akio Nishida , Kota Funayama , Tomonori Sekiguchi
发明人： Norikatsu Takaura , Hideyuki Matsuoka , Riichiro Takemura , Kousuke Okuyama , Masahiro Moniwa , Akio Nishida , Kota Funayama , Tomonori Sekiguchi
IPC分类号： G11C11/41 , H01L21/8234 , H01L21/8244 , H01L27/00 , H01L27/06 , H01L27/088 , H01L27/10 , H01L27/11 , H01L29/10
CPC分类号： H01L27/11 , H01L27/0688 , H01L27/1104
摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.
摘要翻译：本发明提供一种包括多个字线，多个位线以及多个静态存储单元的半导体存储器件，每个静态存储器单元具有第一，第二，第三，第四，第五和第六和第六晶体管。尽管第一，第二，第三和第四晶体管的每个通道与半导体存储器件的衬底垂直地形成。形成第五晶体管和第六晶体管的源极或漏极的半导体区域形成与衬底相反的PN结。根据本发明的另一方面，本发明的SRAM器件具有多个SRAM单元，其中至少一个是在衬底上包括至少四个垂直晶体管的垂直SRAM单元，并且每个垂直晶体管包括源极，排水管和其间的通道在以大于零度的角度穿入衬底表面的一个对准线对中。

8. 发明授权

US06900492B2 Integrated circuit device with P-type gate memory cell having pedestal contact plug and peripheral circuit 失效
标题翻译：具有P型栅极存储单元的集成电路器件具有基座接触插头和外围电路
公开(公告)号：US06900492B2
公开(公告)日：2005-05-31
申请号：US10164008
申请日：2002-06-07
申请人： Norikatsu Takaura , Hideyuki Matsuoka , Shinichiro Kimura , Ryo Nagai , Satoru Yamada
发明人： Norikatsu Takaura , Hideyuki Matsuoka , Shinichiro Kimura , Ryo Nagai , Satoru Yamada
IPC分类号： H01L27/108 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L21/8246 , H01L27/115 , H01L29/49 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10894 , H01L21/76895 , H01L21/76897 , H01L21/823857 , H01L27/10814 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L27/10897 , H01L27/11502 , H01L27/11507 , H01L29/4941 , H01L29/6656
摘要： A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved.Each gate electrode in a memory cell area is formed of p type polycrystalline silicon, and a cap insulating film on each gate electrode and a sidewall film on the sidewall thereof are formed of a silicon oxide film. A polycrystalline silicon film formed on the gate electrodes and between the gate electrodes is polished by a CMP method, and thereby contact electrodes are formed. Also, sidewall films each composed of a laminated film of the silicon oxide film and the polycrystalline silicon film are formed on the sidewall of the gate electrodes in the logic circuit area, and these films are used as a mask to form semiconductor areas. As a result, it is possible to reduce the boron penetration and form contact electrodes in a self-alignment manner. In addition, the performance of the MISFET constituting the logic circuit can be improved.
摘要翻译： DRAM存储单元的刷新特性得到改善，并且在周边形成的构成逻辑电路的MISFET的性能得到改善。存储单元区域中的每个栅电极由p型多晶硅形成，并且每个栅电极上的帽绝缘膜和其侧壁上的侧壁膜由氧化硅膜形成。通过CMP方法对形成在栅电极和栅电极之间的多晶硅膜进行抛光，形成接触电极。此外，在逻辑电路区域中的栅电极的侧壁上形成各自由氧化硅膜和多晶硅膜的叠层膜构成的侧壁膜，并且将这些膜用作掩模以形成半导体区域。结果，可以以自对准的方式降低硼渗透并形成接触电极。此外，可以提高构成逻辑电路的MISFET的性能。

9. 发明申请

US20050208716A1 Semiconductor integrated circuit device and production method thereof 审中-公开
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20050208716A1
公开(公告)日：2005-09-22
申请号：US11130236
申请日：2005-05-17
申请人： Norikatsu Takaura , Hideyuki Matsuoka , Shinichiro Kimura , Ryo Nagai , Satoru Yamada
发明人： Norikatsu Takaura , Hideyuki Matsuoka , Shinichiro Kimura , Ryo Nagai , Satoru Yamada
IPC分类号： H01L27/108 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L21/8246 , H01L27/115 , H01L29/49
CPC分类号： H01L27/10894 , H01L21/76895 , H01L21/76897 , H01L21/823857 , H01L27/10814 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L27/10897 , H01L27/11502 , H01L27/11507 , H01L29/4941 , H01L29/6656
摘要： A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved. Each gate electrode in a memory cell area is formed of p type polycrystalline silicon, and a cap insulating film on each gate electrode and a sidewall film on the sidewall thereof are formed of a silicon oxide film. A polycrystalline silicon film formed on the gate electrodes and between the gate electrodes is polished by a CMP method, and thereby contact electrodes are formed. Also, sidewall films each composed of a laminated film of the silicon oxide film and the polycrystalline silicon film are formed on the sidewall of the gate electrodes in the logic circuit area, and these films are used as a mask to form semiconductor areas. As a result, it is possible to reduce the boron penetration and form contact electrodes in a self-alignment manner. In addition, the performance of the MISFET constituting the logic circuit can be improved.
摘要翻译： DRAM存储单元的刷新特性得到改善，并且在周边形成的构成逻辑电路的MISFET的性能得到改善。存储单元区域中的每个栅电极由p型多晶硅形成，并且每个栅电极上的帽绝缘膜和其侧壁上的侧壁膜由氧化硅膜形成。通过CMP方法对形成在栅电极和栅电极之间的多晶硅膜进行抛光，形成接触电极。此外，在逻辑电路区域中的栅电极的侧壁上形成各自由氧化硅膜和多晶硅膜的叠层膜构成的侧壁膜，并且将这些膜用作掩模以形成半导体区域。结果，可以以自对准的方式降低硼渗透并形成接触电极。此外，可以提高构成逻辑电路的MISFET的性能。

10. 发明授权

US07385838B2 Semiconductor device with a non-erasable memory and/or a nonvolatile memory 失效
标题翻译：具有不可擦除存储器和/或非易失性存储器的半导体器件
公开(公告)号：US07385838B2
公开(公告)日：2008-06-10
申请号：US11715918
申请日：2007-03-09
申请人： Kenichi Osada , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki , Takayuki Kawahara
发明人： Kenichi Osada , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki , Takayuki Kawahara
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/3454 , G11C2013/0092 , G11C2213/82
摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.
摘要翻译：一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。

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