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1. 发明授权

US5285323A Integrated circuit chip having primary and secondary random access memories for a hierarchical cache 失效
标题翻译：集成电路芯片，具有用于分级高速缓存的主和次级随机存取存储器
公开(公告)号：US5285323A
公开(公告)日：1994-02-08
申请号：US61273
申请日：1993-05-13
申请人： Ricky C. Hetherington , Francis X. McKeen , Joseph D. Marci , Tryggve Fossum , Joel S. Emer
发明人： Ricky C. Hetherington , Francis X. McKeen , Joseph D. Marci , Tryggve Fossum , Joel S. Emer
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , Y02B60/1225
摘要： A hierarchical cache memory includes a high-speed primary cache memory and a lower speed secondary cache memory of greater storage capacity than the primary cache memory. To manage a huge number of data lines interconnecting the primary and secondary cache memories, the hierarchical cache memory is integrated on a plurality of integrated circuits which include all of the interconnecting data lines. Each integrated circuit includes a primary memory and a secondary memory for storing and retrieving data transferred over a first data input line and a first data output line that link the primary memory to a central processing unit. At any given time, a multi-bit word is addressed in the secondary memory, and a corresponding multi-bit word is addressed in the primary memory. The primary and secondary memories are interconnected by a first multi-line bus for transferring a multi-bit word read from the secondary memory to the primary memory, and by a second multi-line bus for transferring a multi-bit word read from the primary memory to the secondary memory. The secondary memory is linked to a main memory by a second data output line and a second data input line for sequential transmission of bits to exchange multi-bit words during a writeback and refill operation. In a preferred embodiment, data inputs of the primary memory and the secondary memory are wired in parallel to a serial-parallel shift register that is used as a common write buffer.
摘要翻译：分级缓存存储器包括高于主高速缓冲存储器的高速主缓存存储器和比主高速缓存存储器更大存储容量的较低速次级高速缓冲存储器。为了管理互连主要和次要高速缓冲存储器的大量数据线，分层高速缓冲存储器集成在包括所有互连数据线的多个集成电路上。每个集成电路包括主存储器和辅助存储器，用于存储和检索通过第一数据输入线传送的数据和将主存储器链接到中央处理单元的第一数据输出线。在任何给定的时间，多位字在二级存储器中寻址，并且在主存储器中寻址相应的多位字。主存储器和次存储器通过第一多行总线互连，用于将从副存储器读取的多位字传送到主存储器，以及用于传送从主存储器读取的多位字的第二多行总线内存到二级内存。次存储器通过第二数据输出线和第二数据输入线链接到主存储器，用于在写回和再填充操作期间顺序传输位以交换多位字。在优选实施例中，主存储器和次存储器的数据输入与用作公共写入缓冲器的串行 - 并行移位寄存器并联布线。

2. 发明授权

US4985825A System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer 失效
标题翻译：用于延迟存储器访问异常的处理的系统，直到基于虚拟存储器系统的数字计算机的指令流水线的执行阶段为止
公开(公告)号：US4985825A
公开(公告)日：1991-01-15
申请号：US306866
申请日：1989-02-03
申请人： David A. Webb, Jr. , David B. Fite , Ricky C. Hetherington , Francis X. McKeen , Mark A. Firstenberg , John E. Murray , Dwight P. Manley , Ronald M. Salett , Tryggve Fossum
发明人： David A. Webb, Jr. , David B. Fite , Ricky C. Hetherington , Francis X. McKeen , Mark A. Firstenberg , John E. Murray , Dwight P. Manley , Ronald M. Salett , Tryggve Fossum
IPC分类号： G06F9/38 , G06F11/07 , G06F12/08 , G06F12/10
CPC分类号： G06F9/3865 , G06F11/073 , G06F11/0772 , G06F12/1045
摘要： A technique for processing memory access exceptions along with pre-fetched instructions in a pipelined instruction processing computer system is based upon the concept of pipelining exception information along with other parts of the instruction being executed. In response to the detection of access exceptions at a pipeline stage, corresponding fault information is generated and transferred along the pipeline. The fault information is acted upon only when the instruction reaches the execution stage of the pipeline. Each stage of the instruction pipeline is ported into the front end of a memory unit adapted to perform the virtual-to-physical address translation; each port being provided with storage for virtual addresses accompanying an instruction as well as storage for corresponding fault information. When a memory access exception is encountered at the front end of the memory unit, the fault information generated therefrom is loaded into the storage and the port is prevented from accepting further references.

3. 发明授权

US4888679A Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements 失效
标题翻译：使用高速缓存和主存储器的方法和装置，用于通过预取包括向量数据元素的高速缓存块来进行矢量处理和标量处理
公开(公告)号：US4888679A
公开(公告)日：1989-12-19
申请号：US142794
申请日：1988-01-11
申请人： Tryggve Fossum , Ricky C. Hetherington , David B. Fite, Jr. , Dwight P. Manley , Francis X. McKeen , John E. Murray
发明人： Tryggve Fossum , Ricky C. Hetherington , David B. Fite, Jr. , Dwight P. Manley , Francis X. McKeen , John E. Murray
IPC分类号： G06F12/06 , G06F9/38 , G06F12/02 , G06F12/08 , G06F15/78 , G06F17/16
CPC分类号： G06F15/8069 , G06F12/0207 , G06F12/0855 , G06F9/3455 , G06F9/383
摘要： A main memory and cache suitable for scalar processing are used in connection with a vector processor by issuing prefetch requests in response to the recognition of a vector load instruction. A respective prefetch request is issued for each block containing an element of the vector to be loaded from memory. In response to a prefetch request, the cache is checked for a "miss" and if the cache does not include the required block, a refill request is sent to the main memory. The main memory is configured into a plurality of banks and has a capability of processing multiple references. Therefore the different banks can be referenced simultaneously to prefetch multiple blocks of vector data. Preferably a cache bypass is provided to transmit data directly to the vector processor as the data from the main memory are being stored in the cache. In a preferred embodiment, a vector processor is added to a digital computing system including a scalar processor, a virtual address translation buffer, a main memory and a cache. The scalar processor includes a microcode interpreter which sends a vector load command to the vector processing unit and which also generates vector prefetch requests. The addresses for the data blocks to be prefetched are computed based upon the vector address, the length of the vector and the "stride" or spacing between the addresses of the elements of the vector.
摘要翻译：适用于标量处理的主存储器和缓存器与矢量处理器结合使用以响应于矢量加载指令的识别发出预取请求。为包含要从存储器加载的向量的元素的每个块发出相应的预取请求。响应于预取请求，检查缓存是否存在“未命中”，并且如果高速缓存不包括所需的块，则向主存储器发送补充请求。主存储器被配置成多个存储体并且具有处理多个引用的能力。因此，可以同时引用不同的库来预取多个向量数据块。优选地，提供高速缓存旁路以将数据直接发送到向量处理器，因为来自主存储器的数据正被存储在高速缓存中。在优选实施例中，将向量处理器添加到包括标量处理器，虚拟地址转换缓冲器，主存储器和高速缓存的数字计算系统。标量处理器包括微代码解释器，其向向量处理单元发送向量加载命令，并且还生成向量预取请求。要预取的数据块的地址是基于向量地址，向量的长度和向量元素的地址之间的“stride”或间距来计算的。

4. 发明授权

US5113521A Method and apparatus for handling faults of vector instructions causing memory management exceptions 失效
标题翻译：用于处理导致内存管理异常的向量指令故障的方法和装置
公开(公告)号：US5113521A
公开(公告)日：1992-05-12
申请号：US638149
申请日：1991-01-09
申请人： Francis X. McKeen , Tryggve Fossum , Dileep P. Bhandarkar , Cheryl A. Wiecek
发明人： Francis X. McKeen , Tryggve Fossum , Dileep P. Bhandarkar , Cheryl A. Wiecek
IPC分类号： G06F9/46
CPC分类号： G06F9/462
摘要： A data processing system handles memory management exceptions caused by a faulting vector instruction in a vector processor by halting the execution of the faulting vector instruction being executed when the exception occurred and by setting the state information for the vector processor to acknowledge the presence of the exception and to include information about the suboperation of the vector instruction being executed when the exception occurred. The scalar processor is not interrupted at this time, however. Any other vector instructions executing simutaneously with the faulting vector instruction are allowed to continue so long as those instructions do not require data from the faulting instruction. The faulting partially completed vector instruction resumes execution after the operating system has processed the memory management exception.
摘要翻译：数据处理系统通过停止异常发生时执行的故障向量指令的执行，并且通过设置向量处理器的状态信息来确认异常的存在来处理由矢量处理器中的故障向量指令引起的存储器管理异常并且包括关于当异常发生时正在执行的向量指令的子程序的信息。然而，标量处理器此时不会中断。只要这些指令不需要来自故障指令的数据，允许与故障向量指令同时执行的任何其他向量指令。故障部分完成向量指令在操作系统处理内存管理异常后恢复执行。

5. 发明授权

US5168573A Memory device for storing vector registers 失效
标题翻译：用于存储向量寄存器的存储器件
公开(公告)号：US5168573A
公开(公告)日：1992-12-01
申请号：US328561
申请日：1989-03-24
申请人： Tryggve Fossum , Dwight P. Manley , Francis X. McKeen , Michael M. Tahranian
发明人： Tryggve Fossum , Dwight P. Manley , Francis X. McKeen , Michael M. Tahranian
IPC分类号： G06F9/30 , G06F15/78 , G11C8/16
CPC分类号： G06F9/3013 , G06F15/8084 , G06F9/3012 , G11C8/16
摘要： A vector register provides the capability for simultaneously writing through at least two write ports and simultaneous reading from at least two read ports. In addition, a barber pole technique for storing words from logical vector registers into banks is provided to minimize conflicts.
摘要翻译：向量寄存器提供通过至少两个写入端口同时写入并从至少两个读取端口同时读取的能力。另外，提供了用于将逻辑向量寄存器中的字存储到存储体中的理发杆技术，以最小化冲突。

6. 发明授权

US4980817A Vector register system for executing plural read/write commands concurrently and independently routing data to plural read/write ports 失效
标题翻译：用于同时执行多个读/写命令的矢量寄存器系统，并且独立地将数据路由到多个读/写端口
公开(公告)号：US4980817A
公开(公告)日：1990-12-25
申请号：US93499
申请日：1987-08-31
申请人： Tryggve Fossum , Dwight P. Manley , Francis X. McKeen , Michael M. Tehranian
发明人： Tryggve Fossum , Dwight P. Manley , Francis X. McKeen , Michael M. Tehranian
IPC分类号： G06F17/16 , G06F9/30 , G06F15/78 , G11C8/16
CPC分类号： G06F9/30141 , G06F15/8084 , G06F9/30098 , G06F9/30112 , G06F9/3012 , G06F9/3013 , G11C8/16
摘要： A vector register provides the capability for simultaneously writing through at least two write ports and simultaneously reading from at least two read ports. In addition, a barber pole technique for storing words from logical vector registers into banks is provided to minimize conflicts.
摘要翻译：向量寄存器提供通过至少两个写入端口同时写入并同时从至少两个读取端口读取的能力。另外，提供了用于将逻辑向量寄存器中的字存储到存储体中的理发杆技术，以最小化冲突。

7. 发明授权

US5067069A Control of multiple functional units with parallel operation in a microcoded execution unit 失效
标题翻译：在微型执行单元中并行运行的多功能单元的控制
公开(公告)号：US5067069A
公开(公告)日：1991-11-19
申请号：US306832
申请日：1989-02-03
申请人： Elaine H. Fite , Tryggve Fossum , William R. Grundmann , Francis X. McKeen , Ronald M. Salett
发明人： Elaine H. Fite , Tryggve Fossum , William R. Grundmann , Francis X. McKeen , Ronald M. Salett
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30167 , G06F9/30101 , G06F9/3836 , G06F9/3857 , G06F9/3863 , G06F9/3867 , G06F9/3885
摘要： To increase the performance of a pipelined processor executing various classes of instructions, the classes of instructions are executed by respective functional units which are independently controlled and operated in parallel. The classes of instructions include integer instructions, floating point instructions, multiply instructions, and divide instructions. The integer unit, which also performs shift operations, is controlled by the microcode execution unit to handle the wide variety of integer and shift operations included in a complex, variable-length instruction set. The other functional units need only accept a control command to initiate the operation to be performed by the functional unit. The retiring of the results of the instructions need not be controlled by the microcode execution unit, but instead is delegated to a separate retire unit that services a result queue. When the microcode execution unit determines that a new operation is required, an entry is inserted into the result queue. The entry includes all the information needed by the retire unit to retire the result once the result is available from the respective functional unit. The retire unit services the result queue by reading a tag in the entry at the head of the queue to determine the functional unit that is to provide the result. Once the result is available and the destination specified by the entry is also available, the result is retired in accordance with the entry, and the entry is removed from the queue.

8. 发明授权

US5109495A Method and apparatus using a source operand list and a source operand pointer queue between the execution unit and the instruction decoding and operand processing units of a pipelined data processor 失效
标题翻译：使用源操作列表的方法和装置和执行单元之间的源操作指针和管道解码和操作处理单元的管理数据处理器
公开(公告)号：US5109495A
公开(公告)日：1992-04-28
申请号：US306843
申请日：1989-02-03
申请人： David B. Fite , Tryggve Fossum , William R. Grundmann , Dwight P. Manely , Francis X. McKeen , John E. Murray , Ronald M. Salett , Eileen Samberg , Daniel P. Stirling
发明人： David B. Fite , Tryggve Fossum , William R. Grundmann , Dwight P. Manely , Francis X. McKeen , John E. Murray , Ronald M. Salett , Eileen Samberg , Daniel P. Stirling
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30167 , G06F9/30145 , G06F9/3016 , G06F9/3824 , G06F9/3867
摘要： To execute variable-length instructions independently of instruction preprocessing, a central processing unit is provided with a set of queues in the data and control paths between an instruction unit and an execution unit. The queues include a "fork" queue, a source queue, a destination queue, and a program counter queue. The fork queue contains an entry of control information for each instruction processed by the instruction unit. This control information corresponds to the opcode for the instruction, and preferably it is a microcode "fork" address at which a microcode execution unit begins execution to execute the instruction. The source queue specifies the source operands for the instruction. Preferably the source queue stores source pointers and the operands themselves are included in a separate "source list" in the case of operands fetched from memory or immediate data from the instruction stream, or are the contents of a set of general purpose registers in the execution unit. The destination queue specifies the destination for the instruction, for example, either memory or general purpose registers. The program counter queue contains the starting value of the program counter for each of the instructions passed from the instruction unit to the execution unit. Preferably the queues are large enough to hold control information and data for up to six instructions. The queues therefore shield the execution unit and the instruction unit from each others complexities and provide a buffer to allow for an uneven processing rate in either of them.

9. 发明授权

US5125083A Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system 失效
标题翻译：用于解决管道计算机系统中可变存储器访问冲突的可变数量的方法和装置
公开(公告)号：US5125083A
公开(公告)日：1992-06-23
申请号：US306767
申请日：1989-02-03
申请人： David B. Fite , Tryggve Fossum , Ricky C. Hetherington , John E. Murray , Jr. David A. Webb
发明人： David B. Fite , Tryggve Fossum , Ricky C. Hetherington , John E. Murray , Jr. David A. Webb
IPC分类号： G06F9/38
CPC分类号： G06F9/3816 , G06F9/383 , G06F9/3834
摘要： An operand processing unit delivers a specified address and at least one read/write signal in response to an instruction being a source of destination operand, and delivers the source operand to an execution unit in response to completion of the preprocessing. The execution unit receives the source operand, executes it and delivers the resultant data to memory. A "write queue" receives the write addresses of the destination operands from the operand processing unit, stores the write addresses, and delivers the stored preselected addresses to memory in response to receiving the resultant data corresponding to the preselected address. The addresses of the source operand is compared to the write addresses stored in the write queue, and the operand processing unit is stalled whenever at least one of the write addresses in the write queue is equivalent to the read address. Therefore, fetching of the operand is delayed until the corresponding resultant data has been delivered by the execution unit.

10. 发明授权

US5142631A System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register 失效
标题翻译：系统用于单独读取或写入掩模和生成用于控制访问一般目的寄存器的相关复合掩码
公开(公告)号：US5142631A
公开(公告)日：1992-08-25
申请号：US306773
申请日：1989-02-03
申请人： John E. Murray , Mark A. Firstenberg , David B. Fite , Michael M. McKeon , Wiliam R. Grundmann , David A. Webb, Jr. , Ronald M. Salett , Tryggve Fossum , Dwight P. Manley , Ricky C. Hetherington
发明人： John E. Murray , Mark A. Firstenberg , David B. Fite , Michael M. McKeon , Wiliam R. Grundmann , David A. Webb, Jr. , Ronald M. Salett , Tryggve Fossum , Dwight P. Manley , Ricky C. Hetherington
IPC分类号： G06F9/38
CPC分类号： G06F9/355 , G06F9/345 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： A method is provided for preprocessing multiple instructions prior to execution of such instructions in a digital computer having an instruction decoder, an instruction execution unit, and multiple general purpose registers which are read to produce memory addresses during the preprocessing. The method comprises: (1) avoiding the preprocessing of a current instruction to read a general purpose register to produce a memory address prior to the modification of the contents of that register by a preceding instruction by (a) generating a composite write mask having a bit set for each general purpose register whose contents are to be modified by at least one of a plurality of decoded by not-yet-executed instructions preceding the current instruction, and (b) stalling the preprocessing of the current instruction when a general purpose register to be read by the current instruction is a register having a bit set in the write mask, and/or (2) avoiding the preprocessing of a current instruction which modifies the contents of a general purpose register that is to be read by a preceding instruction by (a) generating a composite read mask having a bit set for each general purpose register to be read by at least one of a plurality of decoded but not-yet-executed instructions preceding the current instruction, and (b) stalling the preprocessing of the current instruction when a general purpose register whose contents are to be modified by the current instruction is a register having a bit set in the read mask.

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