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1. 发明授权

US5142631A System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register 失效
标题翻译：系统用于单独读取或写入掩模和生成用于控制访问一般目的寄存器的相关复合掩码
公开(公告)号：US5142631A
公开(公告)日：1992-08-25
申请号：US306773
申请日：1989-02-03
申请人： John E. Murray , Mark A. Firstenberg , David B. Fite , Michael M. McKeon , Wiliam R. Grundmann , David A. Webb, Jr. , Ronald M. Salett , Tryggve Fossum , Dwight P. Manley , Ricky C. Hetherington
发明人： John E. Murray , Mark A. Firstenberg , David B. Fite , Michael M. McKeon , Wiliam R. Grundmann , David A. Webb, Jr. , Ronald M. Salett , Tryggve Fossum , Dwight P. Manley , Ricky C. Hetherington
IPC分类号： G06F9/38
CPC分类号： G06F9/355 , G06F9/345 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： A method is provided for preprocessing multiple instructions prior to execution of such instructions in a digital computer having an instruction decoder, an instruction execution unit, and multiple general purpose registers which are read to produce memory addresses during the preprocessing. The method comprises: (1) avoiding the preprocessing of a current instruction to read a general purpose register to produce a memory address prior to the modification of the contents of that register by a preceding instruction by (a) generating a composite write mask having a bit set for each general purpose register whose contents are to be modified by at least one of a plurality of decoded by not-yet-executed instructions preceding the current instruction, and (b) stalling the preprocessing of the current instruction when a general purpose register to be read by the current instruction is a register having a bit set in the write mask, and/or (2) avoiding the preprocessing of a current instruction which modifies the contents of a general purpose register that is to be read by a preceding instruction by (a) generating a composite read mask having a bit set for each general purpose register to be read by at least one of a plurality of decoded but not-yet-executed instructions preceding the current instruction, and (b) stalling the preprocessing of the current instruction when a general purpose register whose contents are to be modified by the current instruction is a register having a bit set in the read mask.

2. 发明授权

US4985825A System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer 失效
标题翻译：用于延迟存储器访问异常的处理的系统，直到基于虚拟存储器系统的数字计算机的指令流水线的执行阶段为止
公开(公告)号：US4985825A
公开(公告)日：1991-01-15
申请号：US306866
申请日：1989-02-03
申请人： David A. Webb, Jr. , David B. Fite , Ricky C. Hetherington , Francis X. McKeen , Mark A. Firstenberg , John E. Murray , Dwight P. Manley , Ronald M. Salett , Tryggve Fossum
发明人： David A. Webb, Jr. , David B. Fite , Ricky C. Hetherington , Francis X. McKeen , Mark A. Firstenberg , John E. Murray , Dwight P. Manley , Ronald M. Salett , Tryggve Fossum
IPC分类号： G06F9/38 , G06F11/07 , G06F12/08 , G06F12/10
CPC分类号： G06F9/3865 , G06F11/073 , G06F11/0772 , G06F12/1045
摘要： A technique for processing memory access exceptions along with pre-fetched instructions in a pipelined instruction processing computer system is based upon the concept of pipelining exception information along with other parts of the instruction being executed. In response to the detection of access exceptions at a pipeline stage, corresponding fault information is generated and transferred along the pipeline. The fault information is acted upon only when the instruction reaches the execution stage of the pipeline. Each stage of the instruction pipeline is ported into the front end of a memory unit adapted to perform the virtual-to-physical address translation; each port being provided with storage for virtual addresses accompanying an instruction as well as storage for corresponding fault information. When a memory access exception is encountered at the front end of the memory unit, the fault information generated therefrom is loaded into the storage and the port is prevented from accepting further references.

3. 发明授权

US5142634A Branch prediction 失效
标题翻译：分行预测
公开(公告)号：US5142634A
公开(公告)日：1992-08-25
申请号：US306760
申请日：1989-02-03
申请人： David B. Fite , John E. Murray , Dwight P. Manley , Michael M. McKeon , Elaine H. Fite , Ronald M. Salett , Tryggve Fossum
发明人： David B. Fite , John E. Murray , Dwight P. Manley , Michael M. McKeon , Elaine H. Fite , Ronald M. Salett , Tryggve Fossum
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3844
摘要： A branch prediction is made by searching a cache memory for branch history information associated with a branch instruction. If associated information is not found in the cache, then the branch is predicted based on a predetermined branch bias for the branch instruction's opcode; otherwise, the branch is predicted based upon the associated information from the cache. The associated information in the cache preferably includes a length, displacement, and target address in addition to a prediction bit. If the cache includes associated information predicting that the branch will be taken, the target address from cache is used so long as the associated length and displacement match and the length and displacement for the branch instruction; otherwise, the target address must be computed.

4. 发明授权

US5019965A Method and apparatus for increasing the data storage rate of a computer system having a predefined data path width 失效
标题翻译：用于增加具有预定数据路径宽度的计算机系统的数据存储速率的方法和装置
公开(公告)号：US5019965A
公开(公告)日：1991-05-28
申请号：US306826
申请日：1989-02-03
申请人： David A. Webb, Jr. , Ricky C. Hetherington , Ronald M. Salett , Trvggve Fossum , Dwight P. Manley
发明人： David A. Webb, Jr. , Ricky C. Hetherington , Ronald M. Salett , Trvggve Fossum , Dwight P. Manley
IPC分类号： G06F12/08 , G06F13/40
CPC分类号： G06F12/0886 , G06F13/4018
摘要： In a computer system, the flow of data from the execution unit to the cache 28 is enhanced by pairing individual, sequential longword write operations into a simultaneous quadword write operation. Primary and secondary writebuffers 50, 52 sequentially receive the individual longwords during first and second clock cycles and simultaneously present the individual longwords over a quadword wide bus to the cache 28. During the first clock cycle, when the cache 28 is not performing the quadword write operation, the cache 28 is free to perform the requisite lookup routine on the address of the first longword of data to determine if the quadword of address space is available in the cache. Thus, the flow of data to the cache 28 is maximized.

5. 发明授权

US4982402A Method and apparatus for detecting and correcting errors in a pipelined computer system 失效
标题翻译：用于检测和纠正流水线计算机系统中的错误的方法和装置
公开(公告)号：US4982402A
公开(公告)日：1991-01-01
申请号：US306828
申请日：1989-02-03
申请人： Richard C. Beaven , Michael B. Evans , Tryggve Fossum , Ricky C. Hetherington , William R. Grundmann , John E. Murray , Ronald M. Salett
发明人： Richard C. Beaven , Michael B. Evans , Tryggve Fossum , Ricky C. Hetherington , William R. Grundmann , John E. Murray , Ronald M. Salett
IPC分类号： G06F9/38 , G06F11/07 , G06F11/14 , G06F11/267 , G06F15/16 , G06F15/177
CPC分类号： G06F11/2236 , G06F11/0724 , G06F11/0772 , G06F11/0781 , G06F11/1405 , G06F9/3863
摘要： In a multiprocessor system, an error occurring in any one of the CPUs may have an impact upon the operation of the remaining CPUs, and therefore these errors must be handled quickly. The errors are grouped into two categories: synchronous errors (those that must be corrected immediately to allow continued processing of the current instruction); and asynchronous errors (those errors that do not affect execution of the current instruction and may be handled upon completing execution of the current instruction). Since synchronous errors prevent continued execution of the current instruction, it is preferable that the last stable state conditions of the faulting CPU be restored and the faulting instruction reexecuted. These stable state conditions advantageously occur between the execution of each instruction. However, in a pipelined computer system, it is difficult to identify the beginning and ending of a selected instruction since multiple instructions are in process at the same time. Accordingly, the execution unit is selected to be the point of synchronization between error handling and instruction execution. Once the error is indentified as asynchronous or synchronous and the execution unit allows the instruction to complete or rolls back the state conditions to their preinstruction values, error analyzing software examines the condition of the suspect data latches in the CPU. A serial diagnostic link stops the system clock of the CPU and serially loads the CPU data latches into the System Processor Unit for error determination. Thereafter, the CPU system clock is restarted and the CPU resumes execution.

6. 发明授权

US5109495A Method and apparatus using a source operand list and a source operand pointer queue between the execution unit and the instruction decoding and operand processing units of a pipelined data processor 失效
标题翻译：使用源操作列表的方法和装置和执行单元之间的源操作指针和管道解码和操作处理单元的管理数据处理器
公开(公告)号：US5109495A
公开(公告)日：1992-04-28
申请号：US306843
申请日：1989-02-03
申请人： David B. Fite , Tryggve Fossum , William R. Grundmann , Dwight P. Manely , Francis X. McKeen , John E. Murray , Ronald M. Salett , Eileen Samberg , Daniel P. Stirling
发明人： David B. Fite , Tryggve Fossum , William R. Grundmann , Dwight P. Manely , Francis X. McKeen , John E. Murray , Ronald M. Salett , Eileen Samberg , Daniel P. Stirling
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30167 , G06F9/30145 , G06F9/3016 , G06F9/3824 , G06F9/3867
摘要： To execute variable-length instructions independently of instruction preprocessing, a central processing unit is provided with a set of queues in the data and control paths between an instruction unit and an execution unit. The queues include a "fork" queue, a source queue, a destination queue, and a program counter queue. The fork queue contains an entry of control information for each instruction processed by the instruction unit. This control information corresponds to the opcode for the instruction, and preferably it is a microcode "fork" address at which a microcode execution unit begins execution to execute the instruction. The source queue specifies the source operands for the instruction. Preferably the source queue stores source pointers and the operands themselves are included in a separate "source list" in the case of operands fetched from memory or immediate data from the instruction stream, or are the contents of a set of general purpose registers in the execution unit. The destination queue specifies the destination for the instruction, for example, either memory or general purpose registers. The program counter queue contains the starting value of the program counter for each of the instructions passed from the instruction unit to the execution unit. Preferably the queues are large enough to hold control information and data for up to six instructions. The queues therefore shield the execution unit and the instruction unit from each others complexities and provide a buffer to allow for an uneven processing rate in either of them.

7. 发明授权

US5167026A Simultaneously or sequentially decoding multiple specifiers of a variable length pipeline instruction based on detection of modified value of specifier registers 失效
标题翻译：基于检测指定器寄存器的修改值，同时或顺序地解码可变长度管道指令的多个指定符
公开(公告)号：US5167026A
公开(公告)日：1992-11-24
申请号：US306833
申请日：1989-02-03
申请人： John E. Murray , David B. Fite , Mark A. Firstenberg , Lawrence O. Herman , Ronald M. Salett
发明人： John E. Murray , David B. Fite , Mark A. Firstenberg , Lawrence O. Herman , Ronald M. Salett
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30167 , G06F9/30149 , G06F9/30163 , G06F9/30178 , G06F9/3816 , G06F9/3822 , G06F9/3824 , G06F9/3863
摘要： In a pipeline processor, simultaneous decoding of multiple specifiers in a variable-length instruction causes a peculiar problem of an intra-instruction read conflict that occurs whenever an instruction includes an autoincrement or an autodecrement specifier which references either directly or indirectly a register specified by a previously occurring specifier for the current instruction. To avoid stalls during the preprocessing of instructions by the instruction unit, register pointers rather than register data are usually passed to the excellent unit because register data is not always available at the time of instruction decoding. If an intra-instruction read conflict exists, however, the operand value specified by the conflicting register specifier is the initial value of the register being incremented or decremented, and this initial value will have been changed by the time that the execution unit executes the instruction. Preferably, the proper initial value is obtained prior to the incrementing or decrementing of the conflicting register by putting the instruction decoder into a special IRC mode in which only one specifier is decoded per cycle, and if a specifier being decoded is a register specifier, the content of the specified register is transmitted to the execution unit. Circuitry for detecting an intra-instruction read conflict is disclosed as well as an efficient method for handling interrupts, exceptions and flushes that may occur during the processing of an instruction having an intra-instruction read conflict.

8. 发明授权

US5067069A Control of multiple functional units with parallel operation in a microcoded execution unit 失效
标题翻译：在微型执行单元中并行运行的多功能单元的控制
公开(公告)号：US5067069A
公开(公告)日：1991-11-19
申请号：US306832
申请日：1989-02-03
申请人： Elaine H. Fite , Tryggve Fossum , William R. Grundmann , Francis X. McKeen , Ronald M. Salett
发明人： Elaine H. Fite , Tryggve Fossum , William R. Grundmann , Francis X. McKeen , Ronald M. Salett
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30167 , G06F9/30101 , G06F9/3836 , G06F9/3857 , G06F9/3863 , G06F9/3867 , G06F9/3885
摘要： To increase the performance of a pipelined processor executing various classes of instructions, the classes of instructions are executed by respective functional units which are independently controlled and operated in parallel. The classes of instructions include integer instructions, floating point instructions, multiply instructions, and divide instructions. The integer unit, which also performs shift operations, is controlled by the microcode execution unit to handle the wide variety of integer and shift operations included in a complex, variable-length instruction set. The other functional units need only accept a control command to initiate the operation to be performed by the functional unit. The retiring of the results of the instructions need not be controlled by the microcode execution unit, but instead is delegated to a separate retire unit that services a result queue. When the microcode execution unit determines that a new operation is required, an entry is inserted into the result queue. The entry includes all the information needed by the retire unit to retire the result once the result is available from the respective functional unit. The retire unit services the result queue by reading a tag in the entry at the head of the queue to determine the functional unit that is to provide the result. Once the result is available and the destination specified by the entry is also available, the result is retired in accordance with the entry, and the entry is removed from the queue.

9. 发明授权

US06490276B1 Stackable switch port collapse mechanism 失效
标题翻译：可堆叠交换机端口崩溃机制
公开(公告)号：US06490276B1
公开(公告)日：2002-12-03
申请号：US09107177
申请日：1998-06-29
申请人： Ronald M. Salett , Nicholas Ilyadis , David B. Fite, Jr.
发明人： Ronald M. Salett , Nicholas Ilyadis , David B. Fite, Jr.
IPC分类号： H04Q1100
CPC分类号： H04Q3/0029
摘要： A method and apparatus for providing data communication between stations on a network which optimizes the amount of resources required for a network switch. A first data frame is encoded with a source station identifier for the first station and a source switch identifier for the first switch. The first data frame is sent from the first switch to the second switch. A station list in the second switch is updated to indicate that the first station is associated with the first switch. Subsequent data frames having the same destination as the first switch are sent directly to the second switch. Any switch on the network need only identify the local ports attached to the switch, plus the number of switches on the network. The task of identifying all of the ports on the network is distributed across all switches on the network.
摘要翻译：一种用于在网络上的站之间提供数据通信的方法和装置，其优化网络交换机所需的资源量。用第一站的源站标识符和第一交换机的源交换机标识符对第一数据帧进行编码。第一数据帧从第一交换机发送到第二交换机。更新第二开关中的站列表以指示第一站与第一开关相关联。具有与第一交换机相同的目的地的后续数据帧被直接发送到第二交换机。网络上的任何交换机只需要识别连接到交换机的本地端口，再加上网络上的交换机数量。识别网络上所有端口的任务分布在网络上的所有交换机上。

10. 发明授权

US06496502B1 Distributed multi-link trunking method and apparatus 失效
标题翻译：分布式多链路中继方法和装置
公开(公告)号：US06496502B1
公开(公告)日：2002-12-17
申请号：US09106801
申请日：1998-06-29
申请人： David B. Fite, Jr. , Nicholas Ilyadis , Ronald M. Salett
发明人： David B. Fite, Jr. , Nicholas Ilyadis , Ronald M. Salett
IPC分类号： H04J324
CPC分类号： H04L12/4641 , H04L45/7453 , H04L49/351 , H04L49/354
摘要： A method and apparatus for providing data communication between a source station having multiple connections to a first switch and a destination station having multiple connections to a second switch. A trunk identifier to each port on the first switch and each port on the second switch. A data frame is encoded with the trunk identifier for an ingress port on the first switch. The data frame is sent to the second switch from the first switch. A list of egress ports for the destination station is obtained from a station list contained in the second switch. An egress port is selected from the list of egress ports based upon the source address, destination address and trunk identifier. The data frame is sent to the destination station through the selected egress port.
摘要翻译：一种用于在具有到第一交换机的多个连接的源站和具有到第二交换机的多个连接的目的地站之间提供数据通信的方法和装置。第一个交换机上的每个端口和第二个交换机上的每个端口的中继标识符。数据帧用第一交换机上的入口端口的中继标识符进行编码。数据帧从第一个交换机发送到第二个交换机。从第二交换机中包含的站列表获得目的站的出口端口列表。根据源地址，目的地址和中继标识符，从出口端口列表中选出一个出口端口。数据帧通过选定的出口端口发送到目标站。

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