专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06490276B1 Stackable switch port collapse mechanism 失效
标题翻译：可堆叠交换机端口崩溃机制
公开(公告)号：US06490276B1
公开(公告)日：2002-12-03
申请号：US09107177
申请日：1998-06-29
申请人： Ronald M. Salett , Nicholas Ilyadis , David B. Fite, Jr.
发明人： Ronald M. Salett , Nicholas Ilyadis , David B. Fite, Jr.
IPC分类号： H04Q1100
CPC分类号： H04Q3/0029
摘要： A method and apparatus for providing data communication between stations on a network which optimizes the amount of resources required for a network switch. A first data frame is encoded with a source station identifier for the first station and a source switch identifier for the first switch. The first data frame is sent from the first switch to the second switch. A station list in the second switch is updated to indicate that the first station is associated with the first switch. Subsequent data frames having the same destination as the first switch are sent directly to the second switch. Any switch on the network need only identify the local ports attached to the switch, plus the number of switches on the network. The task of identifying all of the ports on the network is distributed across all switches on the network.
摘要翻译：一种用于在网络上的站之间提供数据通信的方法和装置，其优化网络交换机所需的资源量。用第一站的源站标识符和第一交换机的源交换机标识符对第一数据帧进行编码。第一数据帧从第一交换机发送到第二交换机。更新第二开关中的站列表以指示第一站与第一开关相关联。具有与第一交换机相同的目的地的后续数据帧被直接发送到第二交换机。网络上的任何交换机只需要识别连接到交换机的本地端口，再加上网络上的交换机数量。识别网络上所有端口的任务分布在网络上的所有交换机上。

2. 发明授权

US5619662A Memory reference tagging 失效
标题翻译：内存引用标记
公开(公告)号：US5619662A
公开(公告)日：1997-04-08
申请号：US289613
申请日：1994-08-12
申请人： Simon C. Steely, Jr. , David J. Sager , David B. Fite, Jr.
发明人： Simon C. Steely, Jr. , David J. Sager , David B. Fite, Jr.
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/3863 , G06F9/3012 , G06F9/30141 , G06F9/322 , G06F9/3802 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3848 , G06F9/3855 , G06F9/3857
摘要： A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the instruction processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.
摘要翻译：流水线处理器包括指令盒，其包括寄存器映射器，映射一组指令的寄存器操作数字段和由该组指令馈送的指令调度器，以从指令处理器重新排序指令集的发布。映射的寄存器操作数字段在指令发布之前与重新排序的指令集的相应指令相关联。处理器还包括分支预测表，其将与分支指令相关联的过去历史的存储模式映射到分支指令的更可能的预测方向。处理器还包括与指令调度器相关联的存储器参考标记存储器，使得调度器可以在不知道由存储器参考指令寻址的实际存储器位置的情况下重新排序存储器参考指令。

3. 发明授权

US5519841A Multi instruction register mapper 失效
标题翻译：多指令寄存器映射器
公开(公告)号：US5519841A
公开(公告)日：1996-05-21
申请号：US974776
申请日：1992-11-12
申请人： David J. Sager , Simon C. Steely, Jr. , David B. Fite, Jr.
发明人： David J. Sager , Simon C. Steely, Jr. , David B. Fite, Jr.
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/34
CPC分类号： G06F9/3863 , G06F9/32 , G06F9/3806 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3848 , G06F9/3855 , G06F9/3857
摘要： A pipelined processor includes an instruction unit including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.
摘要翻译：流水线处理器包括指令单元，其包括寄存器映射器，映射一组指令的寄存器操作数字段和由该组指令馈送的指令调度器，以从处理器重新排序指令集的发布。映射的寄存器操作数字段在指令发布之前与重新排序的指令集的相应指令相关联。处理器还包括分支预测表，其将与分支指令相关联的过去历史的存储模式映射到分支指令的更可能的预测方向。处理器还包括与指令调度器相关联的存储器参考标记存储器，使得调度器可以在不知道由存储器参考指令寻址的实际存储器位置的情况下重新排序存储器参考指令。

4. 发明授权

US5963719A Two-pin distributed ethernet bus architecture 失效
公开(公告)号：US5963719A
公开(公告)日：1999-10-05
申请号：US589512
申请日：1996-01-22
申请人： David B. Fite, Jr. , Elaine H. Fite , Ron Salett
发明人： David B. Fite, Jr. , Elaine H. Fite , Ron Salett
IPC分类号： G06F13/368 , G06F13/00 , H04L12/413 , H04L12/44 , H04L12/46
CPC分类号： H04L12/44 , H04L12/4135 , H04L12/46
摘要： An intermodule network bus architecture using only two bus wires to transmit data and module state information. A two-pin bus interface in each network module connected to the bus provides for a distributed arbitration procedure in the event that two or more modules are competing for bus access, and provides a coding scheme under which both data signals and collision announcements are transmitted from module to module through the two-wire bus. The architecture handles multiple distributed repeater modules, as well as other network components such as bridges and routers connected to the same bus. An important aspect of the invention is that multiple bus interfaces function as a distributed state machine, to handle the arbitration process and to provide a consistent framework for detecting and processing data signals and various types of collisions, including receive collisions detected on a single local module port, and transmit collisions involving activity on multiple local ports of one or more modules.

5. 发明授权

US06496502B1 Distributed multi-link trunking method and apparatus 失效
标题翻译：分布式多链路中继方法和装置
公开(公告)号：US06496502B1
公开(公告)日：2002-12-17
申请号：US09106801
申请日：1998-06-29
申请人： David B. Fite, Jr. , Nicholas Ilyadis , Ronald M. Salett
发明人： David B. Fite, Jr. , Nicholas Ilyadis , Ronald M. Salett
IPC分类号： H04J324
CPC分类号： H04L12/4641 , H04L45/7453 , H04L49/351 , H04L49/354
摘要： A method and apparatus for providing data communication between a source station having multiple connections to a first switch and a destination station having multiple connections to a second switch. A trunk identifier to each port on the first switch and each port on the second switch. A data frame is encoded with the trunk identifier for an ingress port on the first switch. The data frame is sent to the second switch from the first switch. A list of egress ports for the destination station is obtained from a station list contained in the second switch. An egress port is selected from the list of egress ports based upon the source address, destination address and trunk identifier. The data frame is sent to the destination station through the selected egress port.
摘要翻译：一种用于在具有到第一交换机的多个连接的源站和具有到第二交换机的多个连接的目的地站之间提供数据通信的方法和装置。第一个交换机上的每个端口和第二个交换机上的每个端口的中继标识符。数据帧用第一交换机上的入口端口的中继标识符进行编码。数据帧从第一个交换机发送到第二个交换机。从第二交换机中包含的站列表获得目的站的出口端口列表。根据源地址，目的地址和中继标识符，从出口端口列表中选出一个出口端口。数据帧通过选定的出口端口发送到目标站。

6. 发明授权

US06226290B1 Method and apparatus for adjusting an interpacket gap using a network device in a data communications network 失效
标题翻译：用于使用数据通信网络中的网络设备来调整间隔间隙的方法和装置
公开(公告)号：US06226290B1
公开(公告)日：2001-05-01
申请号：US09069072
申请日：1998-04-28
申请人： Ronald M. Salett , David B. Fite, Jr. , Nicholas Ilyadis
发明人： Ronald M. Salett , David B. Fite, Jr. , Nicholas Ilyadis
IPC分类号： H04L1228
CPC分类号： H04L45/00 , H04L45/22 , H04L47/22
摘要： A method and an apparatus for adjusting an interpacket gap. In one embodiment, a plurality of network devices are tightly coupled together in series. Data is transmitted and received by the network devices in packets with interpacket gaps interposed between each packet. Buffers are included in each network device to serve as elasticity buffers for the data being transmitted between the network devices. The first upstream network device transmits interpacket gaps having an increased size. Downstream network devices may shrink increased size interpacket gaps to reduced size interpacket gaps if the internal buffers are filled to or above a high water mark. However, downstream network devices are not allowed to shrink the size of reduced size interpacket gaps that are received, even if their internal buffers are filled to or above the high water mark.
摘要翻译：一种用于调整间隔间隙的方法和装置。在一个实施例中，多个网络设备被串联紧密耦合在一起。网络设备以数据包的形式发送和接收数据，数据包间插入每个数据包之间。缓冲器被包括在每个网络设备中，用作在网络设备之间传输的数据的弹性缓冲器。第一上游网络设备发送具有增加的大小的分组间隙。如果内部缓冲器被填充到或高于高水位标记，下游网络设备可能收缩增加的尺寸间隔间隙以减小尺寸间隔间隙。然而，即使下游网络设备的内部缓冲器被填充到高水位标记之上或高于水位标记，也不允许下游网络设备缩小所接收的缩小尺寸的外部间隙间隙的尺寸。

7. 发明授权

US07463625B2 Stackable switch port collapse mechanism 有权
标题翻译：可堆叠交换机端口崩溃机制
公开(公告)号：US07463625B2
公开(公告)日：2008-12-09
申请号：US10230758
申请日：2002-08-29
申请人： Ronald M. Salett , Nicholas Ilyadis , David B. Fite, Jr.
发明人： Ronald M. Salett , Nicholas Ilyadis , David B. Fite, Jr.
IPC分类号： H04Q11/00
CPC分类号： H04Q3/0029
摘要： A method and apparatus for providing data communication between stations on a network which optimizes the amount of resources required for a network switch. A first data frame is encoded with a source station identifier for the first station and a source switch identifier for the first switch. The first data frame is sent from the first switch to the second switch. A station list in the second switch is updated to indicate that the first station is associated with the first switch. Subsequent data frames having the same destination as the first switch are sent directly to the second switch. Any switch on the network need only identify the local ports attached to the switch, plus the number of switches on the network. The task of identifying all of the ports on the network is distributed across all switches on the network.
摘要翻译：一种用于在网络上的站之间提供数据通信的方法和装置，其优化网络交换机所需的资源量。用第一站的源站标识符和第一交换机的源交换机标识符对第一数据帧进行编码。第一数据帧从第一交换机发送到第二交换机。更新第二开关中的站列表以指示第一站与第一开关相关联。具有与第一交换机相同的目的地的后续数据帧被直接发送到第二交换机。网络上的任何交换机只需要识别连接到交换机的本地端口，再加上网络上的交换机数量。识别网络上所有端口的任务分布在网络上的所有交换机上。

8. 发明授权

US6061737A Two-pin distributed ethernet bus architecture 有权
标题翻译：双引脚分布式以太网总线架构
公开(公告)号：US6061737A
公开(公告)日：2000-05-09
申请号：US227800
申请日：1999-01-08
申请人： David B. Fite, Jr. , Elaine H. Fite , Ron Salett
发明人： David B. Fite, Jr. , Elaine H. Fite , Ron Salett
IPC分类号： G06F13/368 , G06F13/00 , H04L12/413 , H04L12/44 , H04L12/46 , H04B3/36
CPC分类号： H04L12/44 , H04L12/4135 , H04L12/46
摘要： An intermodule network bus architecture using only two bus wires to transmit data and module state information. A two-pin bus interface in each network module connected to the bus provides for a distributed arbitration procedure in the event that two or more modules are competing for bus access, and provides a coding scheme under which both data signals and collision announcements are transmitted from module to module through the two-wire bus. The architecture handles multiple distributed repeater modules, as well as other network components such as bridges and routers connected to the same bus. An important aspect of the invention is that multiple bus interfaces function as a distributed state machine, to handle the arbitration process and to provide a consistent framework for detecting and processing data signals and various types of collisions, including receive collisions detected on a single local module port, and transmit collisions involving activity on multiple local ports of one or more modules.
摘要翻译：一种模块化的网络总线结构，仅使用两条总线来传输数据和模块状态信息。连接到总线的每个网络模块中的双引脚总线接口在两个或多个模块竞争总线访问的情况下提供分布式仲裁程序，并提供一种编码方案，在该编码方案下，数据信号和冲突通知都从模块通过双线总线模块。该架构处理多个分布式中继器模块，以及其他网络组件，如连接到同一总线的网桥和路由器。本发明的一个重要方面是多个总线接口用作分布式状态机，以处理仲裁过程并提供用于检测和处理数据信号和各种类型的冲突的一致的框架，包括在单个本地模块上检测到的接收冲突端口，并发送涉及在一个或多个模块的多个本地端口上的活动的冲突。

9. 发明授权

US06252888B1 Method and apparatus providing network communications between devices using frames with multiple formats 失效
标题翻译：在使用具有多种格式的帧的设备之间提供网络通信的方法和装置
公开(公告)号：US06252888B1
公开(公告)日：2001-06-26
申请号：US09060166
申请日：1998-04-14
申请人： David B. Fite, Jr. , Nicholas Ilyadis , Ronald M. Salett
发明人： David B. Fite, Jr. , Nicholas Ilyadis , Ronald M. Salett
IPC分类号： H04J316
CPC分类号： H04L1/0061 , H04L12/4645 , H04L12/467 , H04L2001/0097
摘要： A method and an apparatus providing data communications among network devices using tagged and untagged frame formats. In one embodiment, a virtual local area network (VLAN) is implemented using frames that may be transferred among network devices in both tagged and untagged formats. In one embodiment, the frames are transferred among network switches in an untagged format, independent of whether the source devices sent the frames in a tagged or untagged format. In addition, destination devices may receive frames in either a tagged or an untagged format, independent of whether the source devices originally send the frames a tagged or untagged format. Cyclic redundancy check (CRC) code information contained in the frames as originally sent is left unchanged when transferred among the switches of the VLAN, even though the frames may have been modified prior to transfer among switches. New CRC code information is generated for reformatted frames in the switches containing the outbound ports such that reformatted frames with valid CRC codes are forwarded to destination devices. In the event that a switch receives a corrupt frame from a source device, a corresponding corrupt reformatted frame is forwarded to the destination device from the switch.
摘要翻译：一种使用标记和未标记的帧格式在网络设备之间提供数据通信的方法和装置。在一个实施例中，使用可以在标记和未标记格式的网络设备之间传送的帧来实现虚拟局域网（VLAN）。在一个实施例中，帧以非标记格式在网络交换机之间传送，而与源设备是否以加标签或未标记格式发送帧无关。此外，目的地设备可以接收标记或未标记格式的帧，而不管源设备是否最初以帧标记或未标记格式发送帧。原来发送的帧中包含的循环冗余校验（CRC）代码信息在VLAN的交换机之间传输时保持不变，即使帧在交换机之间传输之前可能被修改。在包含出站端口的交换机中为重新格式化的帧生成新的CRC码信息，使得具有有效CRC码的重新格式化的帧被转发到目的地设备。如果交换机从源设备接收到损坏的帧，则相应的损坏的重新格式化帧将从交换机转发到目标设备。

10. 发明授权

US4888679A Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements 失效
标题翻译：使用高速缓存和主存储器的方法和装置，用于通过预取包括向量数据元素的高速缓存块来进行矢量处理和标量处理
公开(公告)号：US4888679A
公开(公告)日：1989-12-19
申请号：US142794
申请日：1988-01-11
申请人： Tryggve Fossum , Ricky C. Hetherington , David B. Fite, Jr. , Dwight P. Manley , Francis X. McKeen , John E. Murray
发明人： Tryggve Fossum , Ricky C. Hetherington , David B. Fite, Jr. , Dwight P. Manley , Francis X. McKeen , John E. Murray
IPC分类号： G06F12/06 , G06F9/38 , G06F12/02 , G06F12/08 , G06F15/78 , G06F17/16
CPC分类号： G06F15/8069 , G06F12/0207 , G06F12/0855 , G06F9/3455 , G06F9/383
摘要： A main memory and cache suitable for scalar processing are used in connection with a vector processor by issuing prefetch requests in response to the recognition of a vector load instruction. A respective prefetch request is issued for each block containing an element of the vector to be loaded from memory. In response to a prefetch request, the cache is checked for a "miss" and if the cache does not include the required block, a refill request is sent to the main memory. The main memory is configured into a plurality of banks and has a capability of processing multiple references. Therefore the different banks can be referenced simultaneously to prefetch multiple blocks of vector data. Preferably a cache bypass is provided to transmit data directly to the vector processor as the data from the main memory are being stored in the cache. In a preferred embodiment, a vector processor is added to a digital computing system including a scalar processor, a virtual address translation buffer, a main memory and a cache. The scalar processor includes a microcode interpreter which sends a vector load command to the vector processing unit and which also generates vector prefetch requests. The addresses for the data blocks to be prefetched are computed based upon the vector address, the length of the vector and the "stride" or spacing between the addresses of the elements of the vector.
摘要翻译：适用于标量处理的主存储器和缓存器与矢量处理器结合使用以响应于矢量加载指令的识别发出预取请求。为包含要从存储器加载的向量的元素的每个块发出相应的预取请求。响应于预取请求，检查缓存是否存在“未命中”，并且如果高速缓存不包括所需的块，则向主存储器发送补充请求。主存储器被配置成多个存储体并且具有处理多个引用的能力。因此，可以同时引用不同的库来预取多个向量数据块。优选地，提供高速缓存旁路以将数据直接发送到向量处理器，因为来自主存储器的数据正被存储在高速缓存中。在优选实施例中，将向量处理器添加到包括标量处理器，虚拟地址转换缓冲器，主存储器和高速缓存的数字计算系统。标量处理器包括微代码解释器，其向向量处理单元发送向量加载命令，并且还生成向量预取请求。要预取的数据块的地址是基于向量地址，向量的长度和向量元素的地址之间的“stride”或间距来计算的。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式