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1. 发明授权

US5142631A System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register 失效
标题翻译：系统用于单独读取或写入掩模和生成用于控制访问一般目的寄存器的相关复合掩码
公开(公告)号：US5142631A
公开(公告)日：1992-08-25
申请号：US306773
申请日：1989-02-03
申请人： John E. Murray , Mark A. Firstenberg , David B. Fite , Michael M. McKeon , Wiliam R. Grundmann , David A. Webb, Jr. , Ronald M. Salett , Tryggve Fossum , Dwight P. Manley , Ricky C. Hetherington
发明人： John E. Murray , Mark A. Firstenberg , David B. Fite , Michael M. McKeon , Wiliam R. Grundmann , David A. Webb, Jr. , Ronald M. Salett , Tryggve Fossum , Dwight P. Manley , Ricky C. Hetherington
IPC分类号： G06F9/38
CPC分类号： G06F9/355 , G06F9/345 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： A method is provided for preprocessing multiple instructions prior to execution of such instructions in a digital computer having an instruction decoder, an instruction execution unit, and multiple general purpose registers which are read to produce memory addresses during the preprocessing. The method comprises: (1) avoiding the preprocessing of a current instruction to read a general purpose register to produce a memory address prior to the modification of the contents of that register by a preceding instruction by (a) generating a composite write mask having a bit set for each general purpose register whose contents are to be modified by at least one of a plurality of decoded by not-yet-executed instructions preceding the current instruction, and (b) stalling the preprocessing of the current instruction when a general purpose register to be read by the current instruction is a register having a bit set in the write mask, and/or (2) avoiding the preprocessing of a current instruction which modifies the contents of a general purpose register that is to be read by a preceding instruction by (a) generating a composite read mask having a bit set for each general purpose register to be read by at least one of a plurality of decoded but not-yet-executed instructions preceding the current instruction, and (b) stalling the preprocessing of the current instruction when a general purpose register whose contents are to be modified by the current instruction is a register having a bit set in the read mask.

2. 发明授权

US5349651A System for translation of virtual to physical addresses by operating memory management processor for calculating location of physical address in memory concurrently with cache comparing virtual addresses for translation 失效
标题翻译：用于通过操作存储器管理处理器来计算虚拟地址到物理地址的系统，用于计算存储器中的物理地址的位置并与高速缓存比较虚拟地址进行翻译
公开(公告)号：US5349651A
公开(公告)日：1994-09-20
申请号：US746007
申请日：1991-08-09
申请人： Ricky C. Hetherington , David A. Webb, Jr. , David B. Fite , John E. Murray , Tryggve Fossum , Dwight P. Manley
发明人： Ricky C. Hetherington , David A. Webb, Jr. , David B. Fite , John E. Murray , Tryggve Fossum , Dwight P. Manley
IPC分类号： G06F12/08 , G06F12/10 , G06F12/00
CPC分类号： G06F12/0855 , G06F12/1045
摘要： In the field of high speed computers it is common for a central processing unit to reference memory locations via a virtual addressing scheme, rather than by the actual physical memory addresses. In a multi-tasking environment, this virtual addressing scheme reduces the possibility of different programs accessing the same physical memory location. Thus, to maintain computer processing speed, a high speed translation buffer cache is employed to perform the necessary virtual-to-physical conversions for memory reference instructions. The translation buffer cache stores a number of previously translated virtual addresses and their corresponding physical addresses. A memory management processor is employed to update the translation buffer cache with the most recently accessed physical memory locations. The memory management processor consists of a state machine controlling hardware specifically designed for the purpose of updating the translation buffer cache. The memory management processor calculates an address of a location in the memory where the physical address is stored concurrently with the translation buffer cache comparing the virtual address with already stored virtual addresses. With this arrangement the memory management unit can immediately access memory to retrieve the physical address upon a "miss" by the translation buffer cache.
摘要翻译：在高速计算机领域，中央处理单元通常通过虚拟寻址方案而不是实际物理存储器地址来引用存储器位置。在多任务环境中，这种虚拟寻址方案减少了访问相同物理内存位置的不同程序的可能性。因此，为了维持计算机处理速度，使用高速转换缓冲器缓存来对存储器参考指令执行必要的虚拟到物理转换。翻译缓冲区高速缓存存储多个先前转换的虚拟地址及其对应的物理地址。使用存储器管理处理器来更新具有最近访问的物理存储器位置的翻译缓冲器高速缓存。存储器管理处理器由控制硬件的状态机组成，其特别设计用于更新翻译缓冲器高速缓存。存储器管理处理器计算存储器中与物理地址同时存储的位置的地址，该地址与翻译缓冲器高速缓存将虚拟地址与已存储的虚拟地址进行比较。利用这种安排，存储器管理单元可以立即访问存储器，以在翻译缓冲器高速缓存器“遗漏”时检索物理地址。

3. 发明授权

US4985825A System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer 失效
标题翻译：用于延迟存储器访问异常的处理的系统，直到基于虚拟存储器系统的数字计算机的指令流水线的执行阶段为止
公开(公告)号：US4985825A
公开(公告)日：1991-01-15
申请号：US306866
申请日：1989-02-03
申请人： David A. Webb, Jr. , David B. Fite , Ricky C. Hetherington , Francis X. McKeen , Mark A. Firstenberg , John E. Murray , Dwight P. Manley , Ronald M. Salett , Tryggve Fossum
发明人： David A. Webb, Jr. , David B. Fite , Ricky C. Hetherington , Francis X. McKeen , Mark A. Firstenberg , John E. Murray , Dwight P. Manley , Ronald M. Salett , Tryggve Fossum
IPC分类号： G06F9/38 , G06F11/07 , G06F12/08 , G06F12/10
CPC分类号： G06F9/3865 , G06F11/073 , G06F11/0772 , G06F12/1045
摘要： A technique for processing memory access exceptions along with pre-fetched instructions in a pipelined instruction processing computer system is based upon the concept of pipelining exception information along with other parts of the instruction being executed. In response to the detection of access exceptions at a pipeline stage, corresponding fault information is generated and transferred along the pipeline. The fault information is acted upon only when the instruction reaches the execution stage of the pipeline. Each stage of the instruction pipeline is ported into the front end of a memory unit adapted to perform the virtual-to-physical address translation; each port being provided with storage for virtual addresses accompanying an instruction as well as storage for corresponding fault information. When a memory access exception is encountered at the front end of the memory unit, the fault information generated therefrom is loaded into the storage and the port is prevented from accepting further references.

4. 发明授权

US5125083A Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system 失效
标题翻译：用于解决管道计算机系统中可变存储器访问冲突的可变数量的方法和装置
公开(公告)号：US5125083A
公开(公告)日：1992-06-23
申请号：US306767
申请日：1989-02-03
申请人： David B. Fite , Tryggve Fossum , Ricky C. Hetherington , John E. Murray , Jr. David A. Webb
发明人： David B. Fite , Tryggve Fossum , Ricky C. Hetherington , John E. Murray , Jr. David A. Webb
IPC分类号： G06F9/38
CPC分类号： G06F9/3816 , G06F9/383 , G06F9/3834
摘要： An operand processing unit delivers a specified address and at least one read/write signal in response to an instruction being a source of destination operand, and delivers the source operand to an execution unit in response to completion of the preprocessing. The execution unit receives the source operand, executes it and delivers the resultant data to memory. A "write queue" receives the write addresses of the destination operands from the operand processing unit, stores the write addresses, and delivers the stored preselected addresses to memory in response to receiving the resultant data corresponding to the preselected address. The addresses of the source operand is compared to the write addresses stored in the write queue, and the operand processing unit is stalled whenever at least one of the write addresses in the write queue is equivalent to the read address. Therefore, fetching of the operand is delayed until the corresponding resultant data has been delivered by the execution unit.

5. 发明授权

US5113515A Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer 失效
标题翻译：虚拟指令高速缓存系统使用长度响应的指令转换和与预置缓冲区输出的合并来填充指令缓冲区
公开(公告)号：US5113515A
公开(公告)日：1992-05-12
申请号：US306831
申请日：1989-02-03
申请人： David B. Fite , Ricky C. Hetherington , Michael M. McKeon , Dwight P. Manley , John E. Murray
发明人： David B. Fite , Ricky C. Hetherington , Michael M. McKeon , Dwight P. Manley , John E. Murray
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/30149 , G06F9/3816
摘要： An instruction buffer of a high speed digital computer controls the flow of instruction stream to an instruction decoder. The buffer provides the decoder with nine bytes of sequential instruction stream. The instruction set used by the computer is of the variable length type, such that the decoder consumes a variable number of the instruction stream bytes, depending upon the type of instruction being decoded. As each instruction is consumed, a shifter removes the consumed bytes and repositions the remaining bytes into the lowest order positions. The byte positions left empty by the shifter are filled by instruction stream retrieved from one of a pair of prefetch buffers (IBEX, IBEX2) or from a virtual instruction cache. These prefetch buffers are arranged to hold the next two subsequent quadwords of instruction stream and provide the desired missing bytes. The IBEX prefetch buffer is filled from the instruction cache after being emptied, but prior to those particular bytes being requested to fill the instruction decoder. This two level prefetching allows the relatively slow process of cache access to be performed during noncritical time. The instruction decoder is not stalled, waiting for a cache refill, but can ordinarily obtain the desired bytes of instruction stream from the prefetch buffer.

6. 发明授权

US5142634A Branch prediction 失效
标题翻译：分行预测
公开(公告)号：US5142634A
公开(公告)日：1992-08-25
申请号：US306760
申请日：1989-02-03
申请人： David B. Fite , John E. Murray , Dwight P. Manley , Michael M. McKeon , Elaine H. Fite , Ronald M. Salett , Tryggve Fossum
发明人： David B. Fite , John E. Murray , Dwight P. Manley , Michael M. McKeon , Elaine H. Fite , Ronald M. Salett , Tryggve Fossum
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3844
摘要： A branch prediction is made by searching a cache memory for branch history information associated with a branch instruction. If associated information is not found in the cache, then the branch is predicted based on a predetermined branch bias for the branch instruction's opcode; otherwise, the branch is predicted based upon the associated information from the cache. The associated information in the cache preferably includes a length, displacement, and target address in addition to a prediction bit. If the cache includes associated information predicting that the branch will be taken, the target address from cache is used so long as the associated length and displacement match and the length and displacement for the branch instruction; otherwise, the target address must be computed.

7. 发明授权

US5148528A Method and apparatus for simultaneously decoding three operands in a variable length instruction when one of the operands is also of variable length 失效
标题翻译：同时在可变长度指令中同时解码三个操作的方法和装置，其中一个操作也是可变长度
公开(公告)号：US5148528A
公开(公告)日：1992-09-15
申请号：US307347
申请日：1989-02-03
申请人： David B. Fite , John E. Murray , Tryggve Fossum
发明人： David B. Fite , John E. Murray , Tryggve Fossum
IPC分类号： G06F9/32 , G06F9/30 , G06F9/318 , G06F9/34 , G06F9/38
CPC分类号： G06F9/30192 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/34 , G06F9/3816 , G06F9/3822 , G06F9/3838
摘要： An instruction decoder for a pipelined data processing unit simultaneously decodes two source specifiers and one destination specifier. All three of the specifiers can be register specifiers in which the specified operand is the content of a specified register. Any one of the specifiers can be a complex specifier designating an index register, a base register, and a displacement. Any one of the source specifiers can specify short literal data. Data for locating the two source operands and the destination operand are transmitted over parallel buses to an execution unit, so that most instructions are executed at a rate of one instruction per clock cycle. The complex specifier can have a variable length determined by its data type as well as its addressing mode. In particular, the complex specifier may specify a long length of extended immediate data that is received through the instruction buffer over a number of clock cycles.

8. 发明授权

US5109495A Method and apparatus using a source operand list and a source operand pointer queue between the execution unit and the instruction decoding and operand processing units of a pipelined data processor 失效
标题翻译：使用源操作列表的方法和装置和执行单元之间的源操作指针和管道解码和操作处理单元的管理数据处理器
公开(公告)号：US5109495A
公开(公告)日：1992-04-28
申请号：US306843
申请日：1989-02-03
申请人： David B. Fite , Tryggve Fossum , William R. Grundmann , Dwight P. Manely , Francis X. McKeen , John E. Murray , Ronald M. Salett , Eileen Samberg , Daniel P. Stirling
发明人： David B. Fite , Tryggve Fossum , William R. Grundmann , Dwight P. Manely , Francis X. McKeen , John E. Murray , Ronald M. Salett , Eileen Samberg , Daniel P. Stirling
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30167 , G06F9/30145 , G06F9/3016 , G06F9/3824 , G06F9/3867
摘要： To execute variable-length instructions independently of instruction preprocessing, a central processing unit is provided with a set of queues in the data and control paths between an instruction unit and an execution unit. The queues include a "fork" queue, a source queue, a destination queue, and a program counter queue. The fork queue contains an entry of control information for each instruction processed by the instruction unit. This control information corresponds to the opcode for the instruction, and preferably it is a microcode "fork" address at which a microcode execution unit begins execution to execute the instruction. The source queue specifies the source operands for the instruction. Preferably the source queue stores source pointers and the operands themselves are included in a separate "source list" in the case of operands fetched from memory or immediate data from the instruction stream, or are the contents of a set of general purpose registers in the execution unit. The destination queue specifies the destination for the instruction, for example, either memory or general purpose registers. The program counter queue contains the starting value of the program counter for each of the instructions passed from the instruction unit to the execution unit. Preferably the queues are large enough to hold control information and data for up to six instructions. The queues therefore shield the execution unit and the instruction unit from each others complexities and provide a buffer to allow for an uneven processing rate in either of them.

9. 发明授权

US5142633A Preprocessing implied specifiers in a pipelined processor 失效
标题翻译：在管道处理器中预处理暗示指示器
公开(公告)号：US5142633A
公开(公告)日：1992-08-25
申请号：US306846
申请日：1989-02-03
申请人： John E. Murray , David B. Fite , Mark A. Firstenberg
发明人： John E. Murray , David B. Fite , Mark A. Firstenberg
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/30054 , G06F9/30149 , G06F9/30163 , G06F9/30167 , G06F9/30178 , G06F9/34 , G06F9/3816 , G06F9/3822 , G06F9/3824
摘要： An instruction decoder generates implied specifiers for certain predefined instructions, and an operand processing unit preprocess most of the implied specifiers in the same fashion as express operand specifiers. For instructions having an implied autoincrement or autodecrement of the stack pointer, an implied read or write access type is assigned to the instruction and the decode logic is configured accordingly. When an opcode is decoded and is found to have an implied write specifier, a destination operand is created for autodecrementing the stack pointer. If an opcode is decoded and found to have an implied read specifier, a source operand is created for autoincrementing the stack pointer. A register or short literal specifier can be decoded simultaneously with the generation of the implied operand. Therefore some common instructions such as "PUSH Rx" can be decoded in a single cycle. The preprocessing of implied specifiers in addition permits more complex instructions such as "BSR DEST" to be executed in a single cycle. Conflicts created by the implied specifiers are handled in the same manner as conflicts for express specifiers. Moreover, by using the same data paths for both the implied specifiers and the express specifiers, and by inserting queues between the instruction unit and the execution unit, performance gains are realized for instructions having implied specifiers as well as just express specifiers.

10. 发明授权

US5167026A Simultaneously or sequentially decoding multiple specifiers of a variable length pipeline instruction based on detection of modified value of specifier registers 失效
标题翻译：基于检测指定器寄存器的修改值，同时或顺序地解码可变长度管道指令的多个指定符
公开(公告)号：US5167026A
公开(公告)日：1992-11-24
申请号：US306833
申请日：1989-02-03
申请人： John E. Murray , David B. Fite , Mark A. Firstenberg , Lawrence O. Herman , Ronald M. Salett
发明人： John E. Murray , David B. Fite , Mark A. Firstenberg , Lawrence O. Herman , Ronald M. Salett
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30167 , G06F9/30149 , G06F9/30163 , G06F9/30178 , G06F9/3816 , G06F9/3822 , G06F9/3824 , G06F9/3863
摘要： In a pipeline processor, simultaneous decoding of multiple specifiers in a variable-length instruction causes a peculiar problem of an intra-instruction read conflict that occurs whenever an instruction includes an autoincrement or an autodecrement specifier which references either directly or indirectly a register specified by a previously occurring specifier for the current instruction. To avoid stalls during the preprocessing of instructions by the instruction unit, register pointers rather than register data are usually passed to the excellent unit because register data is not always available at the time of instruction decoding. If an intra-instruction read conflict exists, however, the operand value specified by the conflicting register specifier is the initial value of the register being incremented or decremented, and this initial value will have been changed by the time that the execution unit executes the instruction. Preferably, the proper initial value is obtained prior to the incrementing or decrementing of the conflicting register by putting the instruction decoder into a special IRC mode in which only one specifier is decoded per cycle, and if a specifier being decoded is a register specifier, the content of the specified register is transmitted to the execution unit. Circuitry for detecting an intra-instruction read conflict is disclosed as well as an efficient method for handling interrupts, exceptions and flushes that may occur during the processing of an instruction having an intra-instruction read conflict.

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