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1. 发明申请

US20050106788A1 Method and process to make multiple-threshold metal gates CMOS technology 审中-公开
公开(公告)号：US20050106788A1
公开(公告)日：2005-05-19
申请号：US11001913
申请日：2004-12-02
申请人： Ricky Amos , Katayun Barmak , Diane Boyd , Cyril Cabral , Meikei Leong , Thomas Kanarsky , Jakub Kedzierski
发明人： Ricky Amos , Katayun Barmak , Diane Boyd , Cyril Cabral , Meikei Leong , Thomas Kanarsky , Jakub Kedzierski
IPC分类号： H01L27/092 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L31/0392
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823842 , H01L21/84 , H01L29/66545
摘要： Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.

2. 发明授权

US06846734B2 Method and process to make multiple-threshold metal gates CMOS technology 有权
标题翻译：制造多阈值金属门CMOS技术的方法与工艺
公开(公告)号：US06846734B2
公开(公告)日：2005-01-25
申请号：US10300165
申请日：2002-11-20
申请人： Ricky Amos , Katayun Barmak , Diane C. Boyd , Cyril Cabral, Jr. , Meikei Leong , Thomas S. Kanarsky , Jakub Tadeusz Kedzierski
发明人： Ricky Amos , Katayun Barmak , Diane C. Boyd , Cyril Cabral, Jr. , Meikei Leong , Thomas S. Kanarsky , Jakub Tadeusz Kedzierski
IPC分类号： H01L27/092 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L21/3205 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823842 , H01L21/84 , H01L29/66545
摘要： Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.
摘要翻译：提供了形成具有易于调节的多阈值电压的互补金属氧化物半导体（CMOS）器件的方法。提供了用金属双层（代表本发明的第一种方法）或金属合金（代表本发明的第二种方法）的总的水杨酸化。还描述了通过本方法提供的具有多阈值电压的CMOS器件。

3. 发明申请

US20060189061A1 CMOS silicide metal gate integration 有权
标题翻译： CMOS硅化物金属栅极集成
公开(公告)号：US20060189061A1
公开(公告)日：2006-08-24
申请号：US11407313
申请日：2006-04-19
申请人： Ricky Amos , Diane Boyd , Cyril Cabral , Richard Kaplan , Jakub Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda Mocuta , Vijay Narayanan , An Steegen , Maheswaren Surendra
发明人： Ricky Amos , Diane Boyd , Cyril Cabral , Richard Kaplan , Jakub Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda Mocuta , Vijay Narayanan , An Steegen , Maheswaren Surendra
IPC分类号： H01L21/8238
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要翻译：本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

4. 发明申请

US20050186747A1 CMOS silicide metal gate integration 失效
标题翻译： CMOS硅化物金属栅极集成
公开(公告)号：US20050186747A1
公开(公告)日：2005-08-25
申请号：US10786901
申请日：2004-02-25
申请人： Ricky Amos , Diane Boyd , Cyril Cabral , Richard Kaplan , Jakub Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda Mocuta , Vijay Narayanan , An Steegen , Maheswaran Surendra
发明人： Ricky Amos , Diane Boyd , Cyril Cabral , Richard Kaplan , Jakub Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda Mocuta , Vijay Narayanan , An Steegen , Maheswaran Surendra
IPC分类号： H01L21/28 , H01L21/336 , H01L21/339 , H01L21/60 , H01L21/8238
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要翻译：本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

5. 发明申请

US20050064690A1 PROCESS OPTIONS OF FORMING SILICIDED METAL GATES FOR ADVANCED CMOS DEVICES 失效
标题翻译：用于高级CMOS器件形成硅化金属栅的工艺选择
公开(公告)号：US20050064690A1
公开(公告)日：2005-03-24
申请号：US10605261
申请日：2003-09-18
申请人： Ricky Amos , Douglas Buchanan , Cyril Cabral , Evgeni Gousev , Victor Ku , An Steegen
发明人： Ricky Amos , Douglas Buchanan , Cyril Cabral , Evgeni Gousev , Victor Ku , An Steegen
IPC分类号： H01L21/768 , H01L21/8238 , H01L21/4763
CPC分类号： H01L21/823842 , H01L21/76895 , H01L21/823835
摘要： Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds. A second silicide may be employed within the gate. A replacement gate is made from two different metals (dual metal gate replacement) prior to capping with a silicide.
摘要翻译：硅化物通过不同的工艺选择被引入到CMOS器件的栅极区域，用于常规和替代栅极类型工艺。将硅化物放置在栅极本身中，引入硅化物直接与栅极电介质接触，将硅化物作为填充物引入金属栅极顶部，并准备就绪，并将硅化物作为覆盖层引入到多晶硅上或现有的金属门。硅化物用作连接CMOS结构的PFET和NFET器件的选项。该过程保护金属栅极，同时允许源极和漏极硅化物与栅极硅化物不同的硅化物。提供了具有栅极和源极和漏极区域的半导体衬底。栅极电介质层与金属栅极层一起沉积在衬底上。然后用形成在栅极顶部上的硅化物对金属栅极层进行封装，然后继续进行常规的器件形成。可以在栅极内使用第二硅化物。在使用硅化物封盖之前，更换栅极由两种不同的金属（双金属栅极替代）制成。

6. 发明授权

US07863083B2 High temperature processing compatible metal gate electrode for pFETS and methods for fabrication 有权
标题翻译：用于pFETS的高温处理兼容金属栅电极及其制造方法
公开(公告)号：US07863083B2
公开(公告)日：2011-01-04
申请号：US12197845
申请日：2008-08-25
申请人： Ricky Amos , Douglas A. Buchanan , Cyril Cabral, Jr. , Alessandro C. Callegari , Supratik Guha , Hyungjun Kim , Fenton R. McFeely , Vijay Narayanan , Kenneth P. Rodbell , John J. Yurkas
发明人： Ricky Amos , Douglas A. Buchanan , Cyril Cabral, Jr. , Alessandro C. Callegari , Supratik Guha , Hyungjun Kim , Fenton R. McFeely , Vijay Narayanan , Kenneth P. Rodbell , John J. Yurkas
IPC分类号： H01L21/00 , H01L21/76 , H01L21/266 , H01L21/425
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/3003
摘要： A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.
摘要翻译：描述了通过使用Re，Rh，Pt，Ir或Ru金属制造CMOS栅电极的方法和包含这种栅电极的CMOS结构。这些金属的工作功能使其与当前的pFET要求兼容。例如，金属可以承受生产适当钝化界面而不经历化学变化所需的高氢气压力。金属在介电层上的热稳定性如SiO 2，Al 2 O 3和其它合适的介电材料使其与后处理温度高达1000℃相兼容。具有Re2（CO）10作为源的低温/低压CVD技术当Re沉积时使用材料。

7. 发明申请

US20060105515A1 Process options of forming silicided metal gates for advanced CMOS devices 有权
公开(公告)号：US20060105515A1
公开(公告)日：2006-05-18
申请号：US11271032
申请日：2005-11-10
申请人： Ricky Amos , Douglas Buchanan , Cyril Cabral , Evgeni Gousev , Victor Ku , An Steegen
发明人： Ricky Amos , Douglas Buchanan , Cyril Cabral , Evgeni Gousev , Victor Ku , An Steegen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/76895 , H01L21/823835
摘要： Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds. A second silicide may be employed within the gate. A replacement gate is made from two different metals (dual metal gate replacement) prior to capping with a silicide.

8. 发明申请

US20080311745A1 High Temperature Processing Compatible Metal Gate Electrode For pFETS and Methods For Fabrication 有权
标题翻译：用于pFET的高温加工兼容金属栅电极和制造方法
公开(公告)号：US20080311745A1
公开(公告)日：2008-12-18
申请号：US12197845
申请日：2008-08-25
申请人： Ricky Amos , Douglas A. Buchanan , Cyril Cabral, JR. , Alessandro C. Callegari , Supratik Guha , Hyungjun Kim , Fenton R. McFeely , Vijay Narayanan , Kenneth P. Rodbell , John J. Yurkas
发明人： Ricky Amos , Douglas A. Buchanan , Cyril Cabral, JR. , Alessandro C. Callegari , Supratik Guha , Hyungjun Kim , Fenton R. McFeely , Vijay Narayanan , Kenneth P. Rodbell , John J. Yurkas
IPC分类号： H01L21/44
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/3003
摘要： A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.
摘要翻译：描述了通过使用Re，Rh，Pt，Ir或Ru金属制造CMOS栅电极的方法和包含这种栅电极的CMOS结构。这些金属的工作功能使其与当前的pFET要求兼容。例如，金属可以承受生产适当钝化界面而不经历化学变化所需的高氢气压力。金属在介电层上的热稳定性如SiO 2，Al 2 O 3和其它合适的介电材料使其与后处理温度高达1000℃相兼容。具有Re2（CO）10作为源的低温/低压CVD技术当Re沉积时使用材料。

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