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1. 发明申请

US20060189061A1 CMOS silicide metal gate integration 有权
标题翻译： CMOS硅化物金属栅极集成
公开(公告)号：US20060189061A1
公开(公告)日：2006-08-24
申请号：US11407313
申请日：2006-04-19
申请人： Ricky Amos , Diane Boyd , Cyril Cabral , Richard Kaplan , Jakub Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda Mocuta , Vijay Narayanan , An Steegen , Maheswaren Surendra
发明人： Ricky Amos , Diane Boyd , Cyril Cabral , Richard Kaplan , Jakub Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda Mocuta , Vijay Narayanan , An Steegen , Maheswaren Surendra
IPC分类号： H01L21/8238
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要翻译：本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

2. 发明申请

US20050186747A1 CMOS silicide metal gate integration 失效
标题翻译： CMOS硅化物金属栅极集成
公开(公告)号：US20050186747A1
公开(公告)日：2005-08-25
申请号：US10786901
申请日：2004-02-25
申请人： Ricky Amos , Diane Boyd , Cyril Cabral , Richard Kaplan , Jakub Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda Mocuta , Vijay Narayanan , An Steegen , Maheswaran Surendra
发明人： Ricky Amos , Diane Boyd , Cyril Cabral , Richard Kaplan , Jakub Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda Mocuta , Vijay Narayanan , An Steegen , Maheswaran Surendra
IPC分类号： H01L21/28 , H01L21/336 , H01L21/339 , H01L21/60 , H01L21/8238
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要翻译：本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

3. 发明授权

US07655557B2 CMOS silicide metal gate integration 失效
标题翻译： CMOS硅化物金属栅极集成
公开(公告)号：US07655557B2
公开(公告)日：2010-02-02
申请号：US12145113
申请日：2008-06-24
申请人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
发明人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要翻译：本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

4. 发明授权

US07411227B2 CMOS silicide metal gate integration 有权
标题翻译： CMOS硅化物金属栅极集成
公开(公告)号：US07411227B2
公开(公告)日：2008-08-12
申请号：US11407313
申请日：2006-04-19
申请人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
发明人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
IPC分类号： H01L27/10 , H01L29/73
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要翻译：本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

5. 发明申请

US20080254622A1 CMOS SILICIDE METAL GATE INTEGRATION 失效
标题翻译： CMOS硅胶金属门整合
公开(公告)号：US20080254622A1
公开(公告)日：2008-10-16
申请号：US12145113
申请日：2008-06-24
申请人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
发明人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要翻译：本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

6. 发明授权

US07056782B2 CMOS silicide metal gate integration 失效
公开(公告)号：US07056782B2
公开(公告)日：2006-06-06
申请号：US10786901
申请日：2004-02-25
申请人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaran Surendra
发明人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaran Surendra
IPC分类号： H01L21/8238
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

7. 发明授权

US07776624B2 Method for improving semiconductor surfaces 失效
标题翻译：改善半导体表面的方法
公开(公告)号：US07776624B2
公开(公告)日：2010-08-17
申请号：US12168945
申请日：2008-07-08
申请人： Ashima B. Chakravarti , Judson Robert Holt , Jeremy John Kempisty , Suk Hoon Ku , Woo-Hyeong Lee , Amlan Majumdar , Ryan Matthew Mitchell , Renee Tong Mo , Zhibin Ren , Dinkar Singh
发明人： Ashima B. Chakravarti , Judson Robert Holt , Jeremy John Kempisty , Suk Hoon Ku , Woo-Hyeong Lee , Amlan Majumdar , Ryan Matthew Mitchell , Renee Tong Mo , Zhibin Ren , Dinkar Singh
IPC分类号： H01L21/00
CPC分类号： H01L21/02532 , H01L21/02658 , H01L21/02664 , H01L21/302 , H01L21/30604 , Y10S438/947 , Y10S438/977
摘要： A semiconductor fabrication method. The method includes providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor material. Next, a top portion of the semiconductor substrate is removed. Next, a first semiconductor layer is epitaxially grown on the semiconductor substrate, wherein a first atomic percent of a first semiconductor material in the first semiconductor layer is equal to a substrate atomic percent of the substrate semiconductor material in the semiconductor substrate.
摘要翻译：半导体制造方法。该方法包括提供半导体衬底，其中半导体衬底包括半导体材料。接下来，去除半导体衬底的顶部。接下来，在半导体基板上外延生长第一半导体层，其中第一半导体层中的第一半导体材料的第一原子百分比等于半导体衬底中的衬底半导体材料的衬底原子百分比。

8. 发明申请

US20070087540A1 TRANSISTOR HAVING HIGH MOBILITY CHANNEL AND METHODS 有权
标题翻译：具有高移动通道和方法的晶体管
公开(公告)号：US20070087540A1
公开(公告)日：2007-04-19
申请号：US11557509
申请日：2006-11-08
申请人： Omer Dokumaci , Woo-Hyeong Lee
发明人： Omer Dokumaci , Woo-Hyeong Lee
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/4763
CPC分类号： H01L29/66606 , H01L21/26506 , H01L29/1054 , H01L29/518 , H01L29/66545 , H01L29/66583 , H01L29/7833
摘要： Methods and resulting structure of forming a transistor having a high mobility channel are disclosed. In one embodiment, the method includes providing a gate electrode including a gate material area and a gate dielectric, the gate electrode being positioned over a channel in a silicon substrate. A dielectric layer is formed about the gate electrode, and the gate material area and the gate dielectric are removed from the gate electrode to form an opening into a portion of the silicon substrate that exposes source/drain extensions. A high mobility semiconductor material, i.e., one having a carrier mobility greater than doped silicon, is then formed in the opening such that it laterally contacts the source/drain extensions. The gate dielectric and the gate material area may then be re-formed. This invention eliminates the high temperature steps after the formation of high mobility channel material used in related art methods.
摘要翻译：公开了形成具有高迁移率通道的晶体管的方法和结果。在一个实施例中，该方法包括提供包括栅极材料区域和栅极电介质的栅电极，栅电极位于硅衬底中的沟道上方。在栅电极周围形成电介质层，并且从栅极电极去除栅极材料区域和栅极电介质，以形成露出源极/漏极延伸部分的硅衬底的一部分的开口。然后在开口中形成高迁移率半导体材料，即具有大于掺杂硅的载流子迁移率的高迁移率半导体材料，使得其侧向接触源极/漏极延伸部。然后可以重新形成栅极电介质和栅极材料区域。本发明消除了形成用于相关技术方法的高迁移率通道材料之后的高温步骤。

9. 发明授权

US07119016B2 Deposition of carbon and nitrogen doped poly silicon films, and retarded boron diffusion and improved poly depletion 失效
标题翻译：沉积碳和氮掺杂的多晶硅膜，并延缓硼的扩散和改善的多元消耗
公开(公告)号：US07119016B2
公开(公告)日：2006-10-10
申请号：US10684596
申请日：2003-10-15
申请人： Ashima B. Chakravarti , Anita Madan , Woo-Hyeong Lee , Gregory Wayne Dibello , Ramaseshan Suryanarayanan Iyer
发明人： Ashima B. Chakravarti , Anita Madan , Woo-Hyeong Lee , Gregory Wayne Dibello , Ramaseshan Suryanarayanan Iyer
IPC分类号： H01L21/36
CPC分类号： C23C16/36 , C23C16/24 , H01L21/02532 , H01L21/0262
摘要： A compound that includes at least Si, N and C in any combination, such as compounds of formula (R—NH)4-nSiXn wherein R is an alkyl group (which may be the same or different), n is 1, 2 or 3, and X is H or halogen (such as, e.g., bis-tertiary butyl amino silane (BTBAS)), may be mixed with silane or a silane derivative to produce a film. A polysilicon silicon film may be grown by mixing silane (SiH4) or a silane derviative and a compound including Si, N and C, such as BTBAS. Films controllably doped with carbon and/or nitrogen (such as layered films) may be grown by varying the reagents and conditions.
摘要翻译：至少包含任何组合中的Si，N和C的化合物，例如式（R-NH）4-n-SiX n N的化合物，其中R是烷基（其可以相同或不同），n为1,2或3，X为H或卤素（例如双叔丁基氨基硅烷（BTBAS））可与硅烷或硅烷衍生物混合制作一部电影。可以通过混合硅烷（SiH 4 SO 4）或硅烷衍生物和包括Si，N和C的化合物如BTBAS来生长多晶硅硅膜。可以通过改变试剂和条件来生长可控地掺杂有碳和/或氮的膜（例如层状膜）。

10. 发明申请

US20060166417A1 TRANSISTOR HAVING HIGH MOBILITY CHANNEL AND METHODS 审中-公开
标题翻译：具有高移动通道和方法的晶体管
公开(公告)号：US20060166417A1
公开(公告)日：2006-07-27
申请号：US10905948
申请日：2005-01-27
申请人： Omer Dokumaci , Woo-Hyeong Lee
发明人： Omer Dokumaci , Woo-Hyeong Lee
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L21/26513 , H01L21/26506 , H01L29/1054 , H01L29/518 , H01L29/66545 , H01L29/66583 , H01L29/66606 , H01L29/7833
摘要： Methods and resulting structure of forming a transistor having a high mobility channel are disclosed. In one embodiment, the method includes providing a gate electrode including a gate material area and a gate dielectric, the gate electrode being positioned over a channel in a silicon substrate. A dielectric layer is formed about the gate electrode, and the gate material area and the gate dielectric are removed from the gate electrode to form an opening into a portion of the silicon substrate that exposes source/drain extensions. A high mobility semiconductor material, i.e., one having a carrier mobility greater than doped silicon, is then formed in the opening such that it laterally contacts the source/drain extensions. The gate dielectric and the gate material area may then be re-formed. This invention eliminates the high temperature steps after the formation of high mobility channel material used in related art methods.
摘要翻译：公开了形成具有高迁移率通道的晶体管的方法和结果。在一个实施例中，该方法包括提供包括栅极材料区域和栅极电介质的栅电极，栅电极位于硅衬底中的沟道上方。在栅电极周围形成电介质层，并且从栅极电极去除栅极材料区域和栅极电介质，以形成露出源极/漏极延伸部分的硅衬底的一部分的开口。然后在开口中形成高迁移率半导体材料，即具有大于掺杂硅的载流子迁移率的高迁移率半导体材料，使得其侧向接触源极/漏极延伸部。然后可以重新形成栅极电介质和栅极材料区域。本发明消除了形成用于相关技术方法的高迁移率通道材料之后的高温步骤。

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