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1. 发明授权

US06583479B1 Sidewall NROM and method of manufacture thereof for non-volatile memory cells 有权
标题翻译：侧壁NROM及其制造方法用于非易失性存储单元
公开(公告)号：US06583479B1
公开(公告)日：2003-06-24
申请号：US09688936
申请日：2000-10-16
申请人： Richard M. Fastow , Shane C. Hollmer , Pau-Ling Chen , Michael Van Buskirk , Masaaki Higashitani
发明人： Richard M. Fastow , Shane C. Hollmer , Pau-Ling Chen , Michael Van Buskirk , Masaaki Higashitani
IPC分类号： H01L31062
CPC分类号： H01L27/11568 , B82Y10/00 , G11C16/0458 , G11C16/0475 , G11C16/0491 , G11C16/14 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： An non-volatile read only memory transistor for use in a memory array is disclosed. The non-volatile read only memory transistor features a substantially vertically oriented channel fabricated in a trench formed in the substrate. The channel length is dependent upon the depth of the trench and therefore a dense array of NROM transistors can be formed without adversely affecting the channel length and therefore the operational performance of the transistor.
摘要翻译：公开了一种用于存储器阵列的非易失性只读存储晶体管。非易失性只读存储器晶体管具有在衬底中形成的沟槽中制造的基本上垂直取向的通道。通道长度取决于沟槽的深度，因此可以形成NROM晶体管的密集阵列，而不会不利地影响沟道长度，从而不影响晶体管的操作性能。

2. 发明授权

US5978267A Bit line biasing method to eliminate program disturbance in a non-volatile memory device and memory device employing the same 有权
标题翻译：位线偏置方法，用于消除非易失性存储器件和采用其中的存储器件中的程序干扰
公开(公告)号：US5978267A
公开(公告)日：1999-11-02
申请号：US175647
申请日：1998-10-20
申请人： Pau-Ling Chen , Michael Van Buskirk , Shane C. Hollmer , Michael S. C. Chung , Binh Quang Le , Vincent Leung , Shoichi Kawamura , Masaru Yano
发明人： Pau-Ling Chen , Michael Van Buskirk , Shane C. Hollmer , Michael S. C. Chung , Binh Quang Le , Vincent Leung , Shoichi Kawamura , Masaru Yano
IPC分类号： G11C16/02 , G11C7/12 , G11C16/04 , G11C16/06 , G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C7/12
摘要： In the programming of a non-volatile memory device, such as a NAND flash memory device 100, a positive bias voltage V.sub.bias is applied to a bit line 44 to set a respective memory gate 44a in a programmed state. In a further embodiment, the positive bias voltage V.sub.bias is obtained by dividing the select drain gate voltage V.sub.cc using two resistors 56 and 58 connected in series.
摘要翻译：在非易失性存储器件（例如NAND闪速存储器件100）的编程中，将正偏置电压Vbias施加到位线44以将相应的存储器栅极44a设置为编程状态。在另一实施例中，通过使用串联连接的两个电阻器56和58分压选择漏极栅极电压Vcc来获得正偏置电压Vbias。

3. 发明授权

US06269025B1 Memory system having a program and erase voltage modifier 有权
标题翻译：具有编程和擦除电压调节器的存储器系统
公开(公告)号：US06269025B1
公开(公告)日：2001-07-31
申请号：US09500699
申请日：2000-02-09
申请人： Shane C. Hollmer , Binh Quang Le , Pau-Ling Chen
发明人： Shane C. Hollmer , Binh Quang Le , Pau-Ling Chen
IPC分类号： G11C1604
CPC分类号： G11C5/147 , G11C16/12 , G11C16/16
摘要： A memory system has the capability to adjust a program or erase voltage if the time to program or erase is excessive. The memory system comprises at least a memory cell, a voltage value storage device, a voltage source, and a voltage adjustment circuit. The voltage value storage device stores a voltage value. The voltage source receives and converts the voltage value into a voltage. The voltage source applies the voltage to at least one memory cell. The voltage adjustment circuit is also coupled to receive the stored voltage value. The voltage adjustment circuit determines the time required to program or erase at least one memory cell using the voltage value. If the time to program or erase at least one memory cell is excessive, the voltage adjustment circuit increments the voltage value stored in the voltage value storage device.
摘要翻译：如果编程或擦除时间过长，存储系统可以调整程序或擦除电压。存储器系统至少包括存储器单元，电压值存储器件，电压源和电压调节电路。电压值存储装置存储电压值。电压源接收并将电压值转换为电压。电压源将电压施加到至少一个存储单元。电压调节电路也耦合以接收存储的电压值。电压调节电路使用电压值来确定编程或擦除至少一个存储单元所需的时间。如果编程或擦除至少一个存储单元的时间过长，则电压调节电路增加存储在电压值存储装置中的电压值。

4. 发明授权

US5978266A Array VSS biasing for NAND array programming reliability 失效
标题翻译：阵列VSS偏置用于NAND阵列编程的可靠性
公开(公告)号：US5978266A
公开(公告)日：1999-11-02
申请号：US24880
申请日：1998-02-17
申请人： Pau-ling Chen , Shane C. Hollmer , Binh Q. Le , Michael S. Chung
发明人： Pau-ling Chen , Shane C. Hollmer , Binh Q. Le , Michael S. Chung
IPC分类号： G11C16/04 , G11C16/10
CPC分类号： G11C16/0483 , G11C16/10
摘要： A method is provided for biasing a NAND array EEPROM during programming to allow the array to be scaled down further before reach punchthrough. The sources of the ground-select transistors of the NAND array are biased at V.sub.cc instead of ground to reduce the voltage drop across the source and drain of the ground-select transistors. As a result, the channel length of the ground-select transistors can be further shortened before punchthrough is obtained, resulting in a higher density EEPROM.
摘要翻译：提供了一种用于在编程期间偏置NAND阵列EEPROM以允许阵列在进入穿透之前被进一步缩小的方法。 NAND阵列的接地选择晶体管的源极被偏置为Vcc而不是接地，以减小接地选择晶体管的源极和漏极两端的电压降。结果，在获得穿通之前，可以进一步缩短接地选择晶体管的沟道长度，从而产生更高密度的EEPROM。

5. 发明授权

US06545912B1 Erase verify mode to evaluate negative Vt's 有权
标题翻译：擦除验证模式来评估负Vt
公开(公告)号：US06545912B1
公开(公告)日：2003-04-08
申请号：US09727656
申请日：2000-11-30
申请人： Joseph G. Pawletko , Shane C. Hollmer , Pau-Ling Chen
发明人： Joseph G. Pawletko , Shane C. Hollmer , Pau-Ling Chen
IPC分类号： G11C1606
CPC分类号： G11C29/50004 , G11C16/04 , G11C16/344 , G11C29/50
摘要： A method is provided to determine erase threshold voltages of memory transistors and thereby identify unusable memory transistors. A voltage is applied to the common source of a selected memory transistor and gradually incremented until a logical HIGH bit is read as a logical LOW bit. By iteratively incrementing Vbias, the erase threshold voltage for each memory transistor can be determined. In one process, the erase threshold voltage for each memory transistor in a memory device is determined and then the memory device is put under stress tests to simulate normal operative conditions. After the stress tests, the erase threshold voltage of each memory transistor can be once again determined to ascertain the change in the erase threshold voltage, i.e., the data retention characteristic, of each memory transistor.
摘要翻译：提供了一种方法来确定存储晶体管的擦除阈值电压，从而识别不可用的存储晶体管。电压被施加到所选择的存储晶体管的公共源，并逐渐增加，直到逻辑高位被读为逻辑低位。通过迭代地增加Vbias，可以确定每个存储晶体管的擦除阈值电压。在一个过程中，确定存储器件中每个存储晶体管的擦除阈值电压，然后将存储器件置于压力测试中以模拟正常工作状态。在应力测试之后，可以再次确定每个存储晶体管的擦除阈值电压，以确定每个存储晶体管的擦除阈值电压（即数据保持特性）的变化。

6. 发明授权

US06137153A Floating gate capacitor for use in voltage regulators 失效
标题翻译：用于稳压器的浮栅电容器
公开(公告)号：US06137153A
公开(公告)日：2000-10-24
申请号：US23497
申请日：1998-02-13
申请人： Binh Q. Le , Pau-ling Chen , Shane C. Hollmer
发明人： Binh Q. Le , Pau-ling Chen , Shane C. Hollmer
IPC分类号： H01L29/788 , H01L29/94 , H01L29/00
CPC分类号： H01L29/94 , H01L29/7881
摘要： A capacitor structure which exhibits a constant capacitance at non-negative voltages is provided by erasing a P-well floating gate NMOS transistor prior to its use as a capacitor. By erasing the transistor, a negative threshold voltage is obtained, thereby turning on the transistor and placing the transistor in an inversion state where the MOS capacitance is voltage-independent. Such transistors can be utilized as capacitors, whereby one plate of the capacitor corresponds to the control gate of the transistor and the other plate corresponds to the commonly connected source, drain, P-well, and deep N-well regions of the transistor, in voltage regulator circuits or other circuits in which node stabilization is desired. As a result, the capacitance is constant even at initialization when zero volts is applied.
摘要翻译：在非负电压下呈现恒定电容的电容器结构通过在用作电容器之前擦除P阱浮置NMOS NMOS晶体管来提供。通过擦除晶体管，获得负阈值电压，从而导通晶体管并将晶体管置于MOS电容与电压无关的反转状态。这种晶体管可以用作电容器，由此电容器的一个板对应于晶体管的控制栅极，另一个板对应于晶体管的公共连接的源极，漏极，P阱和深N阱区域，其中电压调节器电路或其中需要节点稳定的其他电路。结果，即使在施加零伏特的初始化时，电容也是恒定的。

7. 发明授权

US5638326A Parallel page buffer verify or read of cells on a word line using a signal from a reference cell in a flash memory device 失效
标题翻译：使用闪存设备中的参考单元的信号，并行页缓冲区验证或读取字线上的单元格
公开(公告)号：US5638326A
公开(公告)日：1997-06-10
申请号：US630919
申请日：1996-04-05
申请人： Shane C. Hollmer , Pau-Ling Chen , Binh Q. Le
发明人： Shane C. Hollmer , Pau-Ling Chen , Binh Q. Le
IPC分类号： G11C7/14 , G11C16/28 , G11C7/00
CPC分类号： G11C7/14 , G11C16/28
摘要： A flash memory including a page buffer with bias circuitry and a reference array enabling reading and verifying values stored on a word line of memory cells in parallel using the page buffer irrespective of temperature, Vcc, and process variations. The bias circuitry includes a cascode transistor having a source connected to the reference cell array which provides a single reference signal. The bias cascode couples the reference signal to an input of a bias inverter in the bias generator, while a bias load transistor in the bias generator couples Vcc to the bias inverter input. The page buffer includes a set of latches that are each coupled to a memory cell by a cascode. A first inverter in each latch has transistors with sizes matching the transistors in the bias inverter. A latch load transistor is connected between a pull-up and pull-down transistor of a second inverter in each latch and is sized to match the bias load transistor. Gates of the bias load transistor and the latch load transistor are both coupled to the output of the bias inverter enabling the first inverter of each latch to have an input mirroring the input of the bias inverter.
摘要翻译：包括具有偏置电路的页缓冲器和参考阵列的闪速存储器，其能够使用页缓冲器并行读取和验证存储单元的字线上的值，而与温度，Vcc和工艺变化无关。偏置电路包括具有连接到参考单元阵列的源的共源共栅晶体管，其提供单个参考信号。偏置共源共栅将参考信号耦合到偏置发生器中的偏置反相器的输入，而偏置发生器中的偏置负载晶体管将Vcc耦合到偏置反相器输入。页面缓冲器包括一组锁存器，每个锁存器通过级联耦合到存储器单元。每个锁存器中的第一个反相器具有与偏置反相器中的晶体管尺寸匹配的晶体管。锁存器负载晶体管连接在每个锁存器中的第二反相器的上拉和下拉晶体管之间，并且其大小适于匹配偏置负载晶体管。偏置负载晶体管和锁存负载晶体管的栅极都耦合到偏置反相器的输出，使得每个锁存器的第一反相器具有镜像偏置反相器的输入的输入。

8. 发明授权

US06373742B1 Two side decoding of a memory array 有权
标题翻译：存储器阵列的双面解码
公开(公告)号：US06373742B1
公开(公告)日：2002-04-16
申请号：US09689036
申请日：2000-10-12
申请人： Kazuhiro Kurihara , Shane C. Hollmer , Pau-Ling Chen
发明人： Kazuhiro Kurihara , Shane C. Hollmer , Pau-Ling Chen
IPC分类号： G11C506
CPC分类号： G11C8/10 , G11C5/025 , G11C5/063
摘要： A decoder for decoding from two sides of a memory array. The decoder is positioned on two sides of the memory array. The decoder includes driver circuits that are connected to routing lines from the memory array. To reduce the size of the decoder, some of the routing lines extend from one side of the memory array and the remaining routing lines extend from the other side of the memory array.
摘要翻译：一种用于从存储器阵列的两侧进行解码的解码器。解码器位于存储器阵列的两侧。解码器包括从存储器阵列连接到路由线路的驱动器电路。为了减小解码器的大小，一些路由线从存储器阵列的一侧延伸，并且剩余的路由线从存储器阵列的另一侧延伸。

9. 发明授权

US6009014A Erase verify scheme for NAND flash 失效
标题翻译：擦除NAND闪存的验证方案
公开(公告)号：US6009014A
公开(公告)日：1999-12-28
申请号：US90296
申请日：1998-06-03
申请人： Shane C. Hollmer , Chung-You Hu , Binh Q. Le , Pau-ling Chen , Jonathan Su , Ravi Gutala , Colin Bill
发明人： Shane C. Hollmer , Chung-You Hu , Binh Q. Le , Pau-ling Chen , Jonathan Su , Ravi Gutala , Colin Bill
IPC分类号： G11C16/04 , G11C16/34 , G11C16/06
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/344
摘要： The present invention provides a method of verifying that all flash EEPROM transistors in a NAND string are properly erased without overerasing by applying a bias voltage to the source of the bottom select gate of the NAND array and applying a non-negative erase verify voltage to the control gates of each transistor during an erase verify. The bias voltage is at least equal to the erased threshold voltage of the worst case transistor to ensure proper erase verification. If all transistors are not erased, then another erase operation is performed. Erasing is repeated until the erase verify operation indicates that all transistors are properly erased. By erasing and verifying according to the present invention, the NAND array is completely and properly erased while minimizing overerasing the array.
摘要翻译：本发明提供了一种验证NAND串中的所有闪存EEPROM晶体管是否被适当地擦除，而不会通过向NAND阵列的底部选择栅极的源施加偏置电压而对其进行过载并向非线性擦除验证电压施加非负的擦除验证电压在擦除验证期间每个晶体管的控制栅极。偏置电压至少等于最坏情况晶体管的擦除阈值电压，以确保正确的擦除验证。如果所有晶体管都不被擦除，则执行另一个擦除操作。重复擦除直到擦除验证操作指示所有晶体管被正确擦除。通过根据本发明的擦除和验证，NAND阵列被完全和适当地擦除，同时使阵列过度减少。

10. 发明授权

US6005804A Split voltage for NAND flash 失效
标题翻译： NAND闪存分压
公开(公告)号：US6005804A
公开(公告)日：1999-12-21
申请号：US993634
申请日：1997-12-18
申请人： Shane C. Hollmer , Binh Quang Le , Pau-ling Chen
发明人： Shane C. Hollmer , Binh Quang Le , Pau-ling Chen
IPC分类号： G11C16/04 , G11C16/10 , G11C16/00
CPC分类号： G11C16/0483 , G11C16/10
摘要： An EEPROM NAND array has floating gate memory cells coupled in series, each having a control gate, a floating gate, a body region, and an insulating layer between the floating gate and the body region. A negative charge pump is coupled to the body region. In programming, the body region of the memory cell selected for programming is biased to a negative voltage by the negative charge pump while the control gate of the memory cell is biased to a predetermined positive voltage sufficient to induce Fowler-Nordheim tunneling from the body region into the floating gate. The present invention allows the programming voltage requirement at the control gate of a NAND EEPROM memory cell to be significantly reduced which allows for the peripheral voltage delivery circuitry in NAND EEPROM arrays to be designed for lower voltages than for conventional NAND EEPROM arrays.
摘要翻译： EEPROM NAND阵列具有串联耦合的浮动栅极存储单元，每个浮动栅极存储单元在浮置栅极和体区之间具有控制栅极，浮动栅极，体区域和绝缘层。负电荷泵耦合到身体区域。在编程中，选择用于编程的存储单元的主体区域被负电荷泵偏置到负电压，而存储单元的控制栅极被偏置到预定的正电压以足以引导来自身体区域的Fowler-Nordheim隧穿进入浮动门。本发明允许NAND EEPROM存储单元的控制栅极上的编程电压要求显着降低，这允许NAND EEPROM阵列中的外围电压传送电路被设计为比传统的NAND EEPROM阵列更低的电压。

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