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1. 发明授权

US6009014A Erase verify scheme for NAND flash 失效
标题翻译：擦除NAND闪存的验证方案
公开(公告)号：US6009014A
公开(公告)日：1999-12-28
申请号：US90296
申请日：1998-06-03
申请人： Shane C. Hollmer , Chung-You Hu , Binh Q. Le , Pau-ling Chen , Jonathan Su , Ravi Gutala , Colin Bill
发明人： Shane C. Hollmer , Chung-You Hu , Binh Q. Le , Pau-ling Chen , Jonathan Su , Ravi Gutala , Colin Bill
IPC分类号： G11C16/04 , G11C16/34 , G11C16/06
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/344
摘要： The present invention provides a method of verifying that all flash EEPROM transistors in a NAND string are properly erased without overerasing by applying a bias voltage to the source of the bottom select gate of the NAND array and applying a non-negative erase verify voltage to the control gates of each transistor during an erase verify. The bias voltage is at least equal to the erased threshold voltage of the worst case transistor to ensure proper erase verification. If all transistors are not erased, then another erase operation is performed. Erasing is repeated until the erase verify operation indicates that all transistors are properly erased. By erasing and verifying according to the present invention, the NAND array is completely and properly erased while minimizing overerasing the array.
摘要翻译：本发明提供了一种验证NAND串中的所有闪存EEPROM晶体管是否被适当地擦除，而不会通过向NAND阵列的底部选择栅极的源施加偏置电压而对其进行过载并向非线性擦除验证电压施加非负的擦除验证电压在擦除验证期间每个晶体管的控制栅极。偏置电压至少等于最坏情况晶体管的擦除阈值电压，以确保正确的擦除验证。如果所有晶体管都不被擦除，则执行另一个擦除操作。重复擦除直到擦除验证操作指示所有晶体管被正确擦除。通过根据本发明的擦除和验证，NAND阵列被完全和适当地擦除，同时使阵列过度减少。

2. 发明授权

US5754475A Bit line discharge method for reading a multiple bits-per-cell flash EEPROM 失效
标题翻译：用于读取多个比特单元的闪存EEPROM的位线放电方法
公开(公告)号：US5754475A
公开(公告)日：1998-05-19
申请号：US884547
申请日：1997-06-27
申请人： Colin Bill , Ravi Gutala , Qimeng (Derek) Zhou , Jonathan Su
发明人： Colin Bill , Ravi Gutala , Qimeng (Derek) Zhou , Jonathan Su
IPC分类号： G11C11/56 , G11C11/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C2211/5622 , G11C2211/5634 , G11C2211/5642
摘要： An improved reading structure (110) for performing a read operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells, each being previously programmed to one of a plurality of memory conditions defined by memory core threshold voltages. A reference cell array (22) includes a plurality of reference core cells which are selected together with a selected core cell and provides selectively one of a plurality of reference cell bit line voltages defined by reference cell threshold voltages. Each of the reference cells are previously programmed at the same time as when the memory core cells are being programmed. A precharge circuit (36) is used to precharge the array bit lines and the reference bit lines to a predetermined potential. A detector circuit (28) is responsive to the bit line voltages of the reference cells for generating strobe signals. A reading circuit (26) is responsive to the strobe signals for comparing the memory core threshold voltage with each of the reference cell threshold voltages.
摘要翻译：提供了一种改进的读取结构（110），用于以多个比特单元的闪存EEPROM存储单元的阵列执行读取操作。存储器核心阵列（12）包括多个存储器单元，每个存储器单元预先被编程为由存储器核心阈值电压定义的多个存储器条件中的一个。参考单元阵列（22）包括与选定的核心单元一起选择的多个参考核心单元，并且选择性地提供由参考单元阈值电压限定的多个参考单元位线电压中的一个。每个参考单元在与存储器核心单元被编程的同时被预先编程。预充电电路（36）用于将阵列位线和参考位线预充电至预定电位。检测器电路（28）响应于参考单元的位线电压以产生选通信号。读取电路（26）响应于选通信号，用于将存储器核心阈值电压与每个参考单元阈值电压进行比较。

3. 发明申请

US20100169740A1 ACCELERATING PHASE CHANGE MEMORY WRITES 有权
标题翻译：加速相变存储器写
公开(公告)号：US20100169740A1
公开(公告)日：2010-07-01
申请号：US12346697
申请日：2008-12-30
申请人： Meenatchi Jagasivamani , Anthony Ko , Rich E. Fackenthal , Ferdinando Bedeschi , Enzo Donze , Ravi Gutala
发明人： Meenatchi Jagasivamani , Anthony Ko , Rich E. Fackenthal , Ferdinando Bedeschi , Enzo Donze , Ravi Gutala
IPC分类号： G11C11/00 , G11C8/00 , H03M13/05 , G06F11/10
CPC分类号： G11C13/0004
摘要： In a phase change memory, the memory array may be written in relatively small chunks. The writing of data to the array and, particularly, the writing of set data, may be accelerated using a hardware accelerator. The hardware accelerator may include an edge detector which detects a short duration signal pulse to trigger the writing of the set data to a cell. As a result, the writing of data may be accelerated, reducing the time to write in some cases.
摘要翻译：在相变存储器中，存储器阵列可以被写入相对小的块。可以使用硬件加速器来加速将数据写入阵列，特别是写入数据。硬件加速器可以包括检测短持续时间信号脉冲以触发将设置数据写入单元的边缘检测器。因此，可能会加速数据的写入，从而减少在某些情况下写入的时间。

4. 发明授权

US08301977B2 Accelerating phase change memory writes 有权
标题翻译：加速相变存储器写入
公开(公告)号：US08301977B2
公开(公告)日：2012-10-30
申请号：US12346697
申请日：2008-12-30
申请人： Meenatchi Jagasivmani , Anthony Ko , Rich E. Fackenthal , Ferdinando Bedeschi , Enzo Donze , Ravi Gutala
发明人： Meenatchi Jagasivmani , Anthony Ko , Rich E. Fackenthal , Ferdinando Bedeschi , Enzo Donze , Ravi Gutala
IPC分类号： G11C29/00
CPC分类号： G11C13/0004
摘要： In a phase change memory, the memory array may be written in relatively small chunks. The writing of data to the array and, particularly, the writing of set data, may be accelerated using a hardware accelerator. The hardware accelerator may include an edge detector which detects a short duration signal pulse to trigger the writing of the set data to a cell. As a result, the writing of data may be accelerated, reducing the time to write in some cases.
摘要翻译：在相变存储器中，存储器阵列可以被写入相对小的块。可以使用硬件加速器来加速将数据写入阵列，特别是写入数据。硬件加速器可以包括检测短持续时间信号脉冲以触发将设置数据写入单元的边缘检测器。因此，可能会加速数据的写入，从而减少在某些情况下写入的时间。

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