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1. 发明授权

US06716046B2 Field effect transistor structure with self-aligned raised source/drain extensions 有权
标题翻译：具有自对准凸起源极/漏极延伸的场效应晶体管结构
公开(公告)号：US06716046B2
公开(公告)日：2004-04-06
申请号：US10209554
申请日：2002-07-30
申请人： Kaizad R. Mistry
发明人： Kaizad R. Mistry
IPC分类号： H01L21336
CPC分类号： H01L29/66621 , H01L29/42376 , H01L29/7834
摘要： Field effect transistor structures include a channel region formed in a recessed portion of a substrate. The recessed channel portion permits the use of relatively thicker source/drain regions thereby providing lower source/drain extension resistivity while maintaining the physical separation needed to overcome various short channel effects. The surface of the recessed channel portion may be of a rectangular, polygonal, or curvilinear shape. In a further aspect of the present invention, transistors are manufactured by a process in which a damascene layer is patterned, the channel region is recessed by etch that is self-aligned to the patterned damascene layer, and the gate electrode is formed by depositing a material over the channel region and patterned damascene layer, polishing off the excess gate electrode material and removing the damascene layer.
摘要翻译：场效应晶体管结构包括形成在衬底的凹陷部分中的沟道区。凹陷通道部分允许使用相对较厚的源极/漏极区域，从而提供更低的源极/漏极延伸电阻率，同时保持克服各种短沟道效应所需的物理分离。凹陷通道部分的表面可以是矩形，多边形或曲线形状。在本发明的另一方面，晶体管是通过图案化的镶嵌层的工艺制造的，沟道区域通过与图案化的镶嵌层自对准的蚀刻凹陷，栅电极通过沉积材料在通道区域和图案化的镶嵌层上，抛光多余的栅电极材料并去除镶嵌层。

2. 发明授权

US06885084B2 Semiconductor transistor having a stressed channel 有权
公开(公告)号：US06885084B2
公开(公告)日：2005-04-26
申请号：US10626257
申请日：2003-07-23
申请人： Anand Murthy , Robert S. Chau , Tahir Ghani , Kaizad R. Mistry
发明人： Anand Murthy , Robert S. Chau , Tahir Ghani , Kaizad R. Mistry
IPC分类号： H01L21/336 , H01L29/10 , H01L29/165 , H01L29/78 , H01L29/06
CPC分类号： H01L29/7848 , H01L21/823814 , H01L27/092 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7842
摘要： A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

3. 发明授权

US06861318B2 Semiconductor transistor having a stressed channel 有权
标题翻译：具有应力通道的半导体晶体管
公开(公告)号：US06861318B2
公开(公告)日：2005-03-01
申请号：US10626365
申请日：2003-07-23
申请人： Anand Murthy , Robert S. Chau , Tahir Ghani , Kaizad R. Mistry
发明人： Anand Murthy , Robert S. Chau , Tahir Ghani , Kaizad R. Mistry
IPC分类号： H01L21/336 , H01L29/10 , H01L29/165 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7848 , H01L21/823814 , H01L27/092 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7842
摘要： A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
摘要翻译：描述了用于制造改进的PMOS半导体晶体管的工艺。凹陷被蚀刻成一层外延硅。源极和漏极膜沉积在凹槽中。源极和漏极膜由硅和锗的合金制成。合金外延沉积在硅层上。合金因此具有与硅层的晶格结构相同结构的晶格。然而，由于包含锗，合金的晶格具有比硅层的晶格间隔更大的间隔。较大的间距在源极和漏极膜之间的晶体管的沟道中产生应力。应力增加晶体管的IDSAT和IDLIN。可以通过包括碳而不是锗来以类似的方式制造NMOS晶体管，从而产生拉伸应力。

4. 发明授权

US6078487A Electro-static discharge protection device having a modulated control input terminal 失效
标题翻译：具有调制控制输入端子的静电放电保护装置
公开(公告)号：US6078487A
公开(公告)日：2000-06-20
申请号：US853840
申请日：1997-05-09
申请人： Hamid Partovi , Kaizad R. Mistry , David B. Krakauer , William A. McGee
发明人： Hamid Partovi , Kaizad R. Mistry , David B. Krakauer , William A. McGee
IPC分类号： H03K17/0814 , H02H9/00
CPC分类号： H01L27/0266 , H03K17/08142
摘要： A circuit which protects an integrated circuit (IC) device from damage due to electrostatic discharge (ESD). The protection circuit includes an N-channel metal oxide semiconductor field effect transistor (MOSFET) clamping device and a gate modulation circuit. The source and drain of the MOSFET clamp are connected between an input/output (I/O) pad of the IC and a ground reference voltage. During normal operation of the IC, the gate modulation circuit disables the MOSFET clamp by connecting its gate terminal to a ground reference voltage. This permits signal voltages to pass between the I/O pad and any operating circuits connected to the pad. During an ESD event, the gate modulation circuit connects the gate to the I/O pad, which enables the MOSFET clamp, causing any ESD voltages and resulting currents to be shunted through the MOSFET clamp to ground. As a result, the ESD clamp reaches its clamped-to snapback voltage via an increase in MOSFET channel current, and not via junction breakdown. This insures that the ESD clamp reaches its snapback voltage before the onset of junction breakdown in the operating circuits. The circuit is especially useful in integrated circuits where the gate oxide of a standard ESD clamp transistor is too thin to protect the operating logic from I/O signal voltages that are greater than the supply voltage used for the operating logic circuits.
摘要翻译：保护集成电路（IC）器件免受静电放电（ESD）损坏的电路。保护电路包括N沟道金属氧化物半导体场效应晶体管（MOSFET）钳位装置和栅极调制电路。 MOSFET钳位的源极和漏极连接在IC的输入/输出（I / O）焊盘和接地参考电压之间。在IC的正常工作期间，栅极调制电路通过将其栅极端子连接到接地参考电压来禁用MOSFET钳位。这允许信号电压在I / O焊盘和连接到焊盘的任何操作电路之间通过。在ESD事件期间，栅极调制电路将栅极连接到I / O焊盘，这使得MOSFET钳位能够使任何ESD电压和所产生的电流通过MOSFET钳位分流到地。因此，ESD钳位通过MOSFET沟道电流的增加而不是通过结击穿而达到其钳位到快速恢复电压。这确保了ESD钳位在工作电路结点击穿开始之前达到其回跳电压。该电路在集成电路中特别有用，其中标准ESD钳位晶体管的栅极氧化物太薄，无法保护操作逻辑免受大于操作逻辑电路所用电源电压的I / O信号电压的影响。

5. 发明授权

US06956263B1 Field effect transistor structure with self-aligned raised source/drain extensions 失效
标题翻译：具有自对准凸起源极/漏极延伸的场效应晶体管结构
公开(公告)号：US06956263B1
公开(公告)日：2005-10-18
申请号：US09473394
申请日：1999-12-28
申请人： Kaizad R. Mistry
发明人： Kaizad R. Mistry
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78 , H01L29/76
CPC分类号： H01L29/66621 , H01L29/42376 , H01L29/7834
摘要： Field effect transistor structures include a channel region formed in a recessed portion of a substrate. The recessed channel portion permits the use of relatively thicker source/drain regions thereby providing lower source/drain extension resistivity while maintaining the physical separation needed to overcome various short channel effects. The surface of the recessed channel portion may be of a rectangular, polygonal, or curvilinear shape. In a further aspect of the present invention, transistors are manufactured by a process in which a damascene layer is patterned, the channel region is recessed by etch that is self-aligned to the patterned damascene layer, and the gate electrode is formed by depositing a material over the channel region and patterned damascene layer, polishing off the excess gate electrode material and removing the damascene layer.
摘要翻译：场效应晶体管结构包括形成在衬底的凹陷部分中的沟道区。凹陷通道部分允许使用相对较厚的源极/漏极区域，从而提供更低的源极/漏极延伸电阻率，同时保持克服各种短沟道效应所需的物理分离。凹陷通道部分的表面可以是矩形，多边形或曲线形状。在本发明的另一方面，晶体管是通过图案化的镶嵌层的工艺制造的，沟道区域通过与图案化的镶嵌层自对准的蚀刻凹陷，栅电极通过沉积材料在通道区域和图案化的镶嵌层上，抛光多余的栅电极材料并去除镶嵌层。

6. 发明授权

US5262344A N-channel clamp for ESD protection in self-aligned silicided CMOS process 失效
标题翻译：用于自对准硅化CMOS工艺中的ESD保护的N沟道钳位
公开(公告)号：US5262344A
公开(公告)日：1993-11-16
申请号：US661707
申请日：1991-02-26
申请人： Kaizad R. Mistry
发明人： Kaizad R. Mistry
IPC分类号： H01L27/02 , H01L29/45 , H01L21/336 , H01L21/72
CPC分类号： H01L29/456 , H01L27/0266
摘要： An ESD protection device is formed in an integrated circuit by an N-channel grounded-gate transistor. This protection device has a polysilicon gate, just as other P- and N-channel transistors in the integrated circuit device, but the siliciding of the protection device is controlled so that adverse effects of ESD events are minimized. There are no silicide areas created on top of the polysilicon gate of the protection device, nor on the source/drain regions near the gate and self-aligned with the gate, as there is for other transistors made by the CMOS process. The siliciding of the protection transistor near the gate is prevented by using a deposited oxide layer as a mask, and this oxide layer is also used to create sidewall spacers for the transistor gates. The sidewall spacers are used in creating self-aligned silicided areas over the source/drain regions, self-aligned with the gates, for all P- and N-channel transistors except the protection transistors. A standard process for making CMOS integrated circuits having self-aligned silicided source/drain areas may be used, with the addition of only one non-critical masking step to block the siliciding of protection transistors.
摘要翻译： ESD保护器件由N沟道接地栅晶体管形成在集成电路中。该保护装置具有多晶硅栅极，就像集成电路器件中的其它P-沟道晶体管和N沟道晶体管一样，但是保护器件的硅化物被控制，使ESD事件的不利影响最小化。在保护器件的多晶硅栅极之上不产生硅化物区域，也不在栅极附近的源极/漏极区域上与栅极自对准，因为由CMOS工艺制造的其它晶体管。通过使用沉积的氧化物层作为掩模来防止栅极附近的保护晶体管的硅化，并且该氧化物层也用于形成用于晶体管栅极的侧壁间隔物。侧壁间隔物用于在除了保护晶体管之外的所有P-沟道晶体管和N沟道晶体管的栅/漏区之上产生自对准硅化物区域。可以使用制造具有自对准硅化物源极/漏极区域的CMOS集成电路的标准工艺，仅添加一个非关键掩模步骤来阻挡保护晶体管的硅化。

7. 发明申请

US20100102356A1 Semiconductor transistor having a stressed channel 审中-公开
标题翻译：具有应力通道的半导体晶体管
公开(公告)号：US20100102356A1
公开(公告)日：2010-04-29
申请号：US12655329
申请日：2009-12-29
申请人： Anand Murthy , Robert S. Chau , Tahir Ghani , Kaizad R. Mistry
发明人： Anand Murthy , Robert S. Chau , Tahir Ghani , Kaizad R. Mistry
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/823814 , H01L27/092 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7842
摘要： A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
摘要翻译：描述了用于制造改进的PMOS半导体晶体管的工艺。凹陷被蚀刻成一层外延硅。源极和漏极膜沉积在凹槽中。源极和漏极膜由硅和锗的合金制成。合金外延沉积在硅层上。合金因此具有与硅层的晶格结构相同结构的晶格。然而，由于包含锗，合金的晶格具有比硅层的晶格间隔更大的间隔。较大的间距在源极和漏极膜之间的晶体管的沟道中产生应力。应力增加晶体管的IDSAT和IDLIN。可以通过包括碳而不是锗来以类似的方式制造NMOS晶体管，从而产生拉伸应力。

8. 发明申请

US20090065808A1 SEMICONDUCTOR TRANSISTOR HAVING A STRESSED CHANNEL 审中-公开
标题翻译：具有应力通道的半导体晶体管
公开(公告)号：US20090065808A1
公开(公告)日：2009-03-12
申请号：US12269829
申请日：2008-11-12
申请人： Anand Murthy , Robert S. Chau , Tahir Ghani , Kaizad R. Mistry
发明人： Anand Murthy , Robert S. Chau , Tahir Ghani , Kaizad R. Mistry
IPC分类号： H01L29/778
CPC分类号： H01L29/7848 , H01L21/823814 , H01L27/092 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7842
摘要： A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
摘要翻译：描述了用于制造改进的PMOS半导体晶体管的工艺。凹陷被蚀刻成一层外延硅。源极和漏极膜沉积在凹槽中。源极和漏极膜由硅和锗的合金制成。合金外延沉积在硅层上。合金因此具有与硅层的晶格结构相同结构的晶格。然而，由于包含锗，合金的晶格具有比硅层的晶格间隔更大的间隔。较大的间距在源极和漏极膜之间的晶体管的沟道中产生应力。应力增加晶体管的IDSAT和IDLIN。可以通过包括碳而不是锗来以类似的方式制造NMOS晶体管，从而产生拉伸应力。

9. 发明授权

US06693331B2 Method of fabricating dual threshold voltage n-channel and p-channel MOSFETS with a single extra masked implant operation 有权
标题翻译：通过单个额外的掩模植入操作制造双阈值电压n沟道和p沟道MOSFET的方法
公开(公告)号：US06693331B2
公开(公告)日：2004-02-17
申请号：US09443056
申请日：1999-11-18
申请人： Kaizad R. Mistry , Ian R. Post
发明人： Kaizad R. Mistry , Ian R. Post
IPC分类号： H01L2976
CPC分类号： H01L21/823807
摘要： A method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions in a substrate, each region having a different doping profile. A conventional two threshold voltage CMOS process is modified to produce four transistor threshold voltages with only one additional masked implant operation. This additional implant raises the threshold voltage of one type of MOSFET while lowering that of the other MOSFET type.
摘要翻译：一种形成MOS集成电路的方法，其具有至少两种类型的具有不同阈值电压的NFET，并且每种类型具有不同阈值电压的至少两种类型的PFET包括在衬底中形成至少四个有源区域，每个区域具有不同的掺杂分布。修改传统的两个阈值电压CMOS工艺以仅产生一个附加的掩模注入操作来产生四个晶体管阈值电压。这种额外的注入提高了一种类型MOSFET的阈值电压，同时降低了另一种MOSFET类型的阈值电压。

10. 发明授权

US5021853A N-channel clamp for ESD protection in self-aligned silicided CMOS process 失效
标题翻译：用于自对准硅化CMOS工艺中的ESD保护的N沟道钳位
公开(公告)号：US5021853A
公开(公告)日：1991-06-04
申请号：US515853
申请日：1990-04-27
申请人： Kaizad R. Mistry
发明人： Kaizad R. Mistry
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/092 , H01L29/45
CPC分类号： H01L27/0266 , H01L29/456 , H01L2924/0002
摘要： An ESD protection device is formed in an integrated circuit by an N-channel grounded-gate transistor. This protection device has a polysilicon gate, just as other P- and N-channel transistors in the integrated circuit device, but the siliciding of the protection device is controlled so that adverse effects of ESD events are minimized. There are no silicide areas created on top of the polysilicon gate of the protection device, nor on the source/drain regions near the gate and self-aligned with the gate, as there is for other transistors made by the CMOS process. The siliciding of the protection transistor near the gate is prevented by using a deposited oxide layer as a mask, and this oxide layer is also used to create sidewall spacers for the transistor gates. The sidewall spacers are used in creating self-aligned silicided areas over the source/drain regions, self-aligned with the gates, for all P- and N-channel transistors except the protection transistors. A standard process for making CMOS integrated circuits having self-aligned silicided source/drain areas may be used, with the addition of only one non-critical masking step to block the siliciding of protection transistors.

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