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1. 发明授权

US5675340A Charge-redistribution analog-to-digital converter with reduced comparator-hysteresis effects 失效
标题翻译：具有降低的比较器滞后效应的电荷再分配模数转换器
公开(公告)号：US5675340A
公开(公告)日：1997-10-07
申请号：US418767
申请日：1995-04-07
申请人： Richard Knight Hester , William J. Bright
发明人： Richard Knight Hester , William J. Bright
IPC分类号： H03M1/06 , H03M1/46 , H03M1/80 , H03M1/12
CPC分类号： H03M1/06 , H03M1/468 , H03M1/804
摘要： Methods and apparatus for an analog-to-digital converter (ADC) with reduced comparator-hysteresis effects. One embodiment uses a charge-redistribution ADC. One method performs an initial coarse analog-to-digital conversion to avoid overdriving an analog voltage comparator. One such method includes a redundant capacitor in an array of charge-redistribution capacitors used in the ADC for sample-and-hold and successive-approximation functions. Another method performs a traditional initial successive-approximation analog-to-digital conversion, and then performs an additional conversion-step test based on the least-significant bit of the initial result to correct for comparator errors in the initial conversion.
摘要翻译：具有降低的比较器滞后效应的模数转换器（ADC）的方法和装置。一个实施例使用电荷再分配ADC。一种方法执行初始粗略模数转换，以避免过驱动模拟电压比较器。一种这样的方法包括在ADC中用于采样和保持和逐次逼近功能的电荷再分配电容器阵列中的冗余电容器。另一种方法执行传统的初始逐次逼近模数转换，然后基于初始结果的最低有效位执行额外的转换步长测试，以校正初始转换中的比较器错误。

2. 发明申请

US20120050081A1 POWER AND AREA EFFICIENT INTERLEAVED ADC 有权
标题翻译：功率和面积有效的交互式ADC
公开(公告)号：US20120050081A1
公开(公告)日：2012-03-01
申请号：US12868539
申请日：2010-08-25
申请人： William J. Bright , Robert F. Payne
发明人： William J. Bright , Robert F. Payne
IPC分类号： H03M1/00 , H03M1/12
CPC分类号： H03M1/1215 , H03M1/1225 , H03M1/164 , H03M1/44
摘要： Pipeline analog-to-digital converters (ADCs) are commonly used for high frequency applications; however, operating at high sampling rates will often result in high power consumption or tight timing constraints. Here, though, an ADC is provided that allows for relaxed timing (which enables a high sampling rate) with low power consumption. This is accomplished through the use of multiplexed, front-end track-and-hold (T/H) circuits that sample on non-overlapping portions of a clocking signal in conjunction with “re-used” or shared analog processing circuitry.
摘要翻译：管道模数转换器（ADC）通常用于高频应用; 然而，以高采样率运行通常会导致高功耗或严格的时序限制。然而，在这里，提供了一种ADC，其具有低功耗的轻松定时（其实现高采样率）。这通过使用多路复用的前端跟踪保持（T / H）电路来实现，该电路在“重用”或共享的模拟处理电路的同时在时钟信号的非重叠部分上进行采样。

3. 发明授权

US06856188B2 Current source/sink with high output impedance using bipolar transistors 有权
标题翻译：使用双极晶体管的具有高输出阻抗的电流源/宿
公开(公告)号：US06856188B2
公开(公告)日：2005-02-15
申请号：US10447176
申请日：2003-05-28
申请人： Marco Corsi , William J. Bright , Martin Kithinji Kinyua
发明人： Marco Corsi , William J. Bright , Martin Kithinji Kinyua
IPC分类号： H03F1/22 , G05F3/26 , G05F1/10
CPC分类号： G05F3/265
摘要： A circuit and method that provides a cascode current source/sink with high output impedance. In one example, the dependency on the external load is reduced by directing a compensation current corresponding to change in base current in the cascode (Q1) in an approach such that the compensation current cancels out the error of the cascode (Q1). In a further example, biasing circuitry (200) is included and arranged such that change in base current of the cascode (Q1) is detected and a corresponding current is summed at the emitter of the cascode (Q1) such that the collector current of the cascode (Q1) remains unchanged.
摘要翻译：提供具有高输出阻抗的共源共栅电流源/宿的电路和方法。在一个示例中，通过在使得补偿电流消除共源共栅（Q1）的误差的方法中引导与共源共栅（Q1）中的基极电流的变化相对应的补偿电流来减小对外部负载的依赖性。在另一示例中，偏置电路（200）被包括并布置成使得检测到共源共栅（Q1）的基极电流的变化，并且在共源共栅（Q1）的发射极处对应的电流相加，使得共源共栅（Q1）保持不变。

4. 发明授权

US07292170B2 System and method for improved time-interleaved analog-to-digital converter arrays 有权
标题翻译：用于改进时间交织的模数转换器阵列的系统和方法
公开(公告)号：US07292170B2
公开(公告)日：2007-11-06
申请号：US11151133
申请日：2005-06-13
申请人： Martin Kithinji Kinyua , William J. Bright
发明人： Martin Kithinji Kinyua , William J. Bright
IPC分类号： H03M3/00
CPC分类号： H03M1/0624 , H03M1/1215
摘要： System and method for improved time-interleaved analog-to-digital converter arrays which reduces sampling mismatch distortion found in prior art arrays. There may be two causes of non-uniform sampling mismatch in a TI-ADC array, a mismatch due to skew and a mismatch due to clock jitter. To minimize non-uniform sampling mismatch, the mismatch due to skew can be addressed. A preferred embodiment comprises adjusting a delay imparted on the sampling clock by an adjustable delay in each channel of a plurality of channels in the TI-ADC array to minimize skew and randomly switching between two delays that span a zero-skew delay to reduce residual skew in each channel and thus eliminate (or reduce) frequency domain tones caused by non-uniform sampling mismatch.
摘要翻译：用于改进时间交织的模数转换器阵列的系统和方法，其减少了现有技术阵列中发现的采样失配失真。在TI-ADC阵列中可能存在两个非均匀采样不匹配的原因：由于偏移引起的失配和由于时钟抖动导致的失配。为了最小化非均匀采样不匹配，可以解决由于偏斜引起的失配。优选实施例包括在TI-ADC阵列中的多个通道的每个通道中调整在采样时钟上施加的延迟一个可调节的延迟，以最小化偏差并在跨越零偏移延迟的两个延迟之间随机切换以减少残余偏斜从而消除（或减少）由不均匀采样失配引起的频域色调。

5. 发明授权

US06618480B1 DAC architecture for analog echo cancellation 失效
标题翻译： DAC架构用于模拟回声消除
公开(公告)号：US06618480B1
公开(公告)日：2003-09-09
申请号：US09070092
申请日：1998-04-30
申请人： Michael O. Polley , William J. Bright
发明人： Michael O. Polley , William J. Bright
IPC分类号： H04M100
CPC分类号： H04B3/23
摘要： Echo cancellation in data communication between modems utilizes analog echo cancellation to lessen reduction of usable dynamic range of the received signal at the input to the analog-to-digital converter (DAC) in the receiver. Two digital-to analog (D/A) conversions are provided in the modem's analog front end (AFE). One generates the analog signal for transmission. The other generates an analog representation of a cancellation signal that is used to electronically cancel the echo before analog-to-digital (A/D) conversion of the received signal. A preferred embodiment utilizes multiplexed DAC architecture to emulate two DACs by sharing DAC circuitry between data paths of the two D/A conversions.
摘要翻译：在调制解调器之间的数据通信中的回波消除利用模拟回声消除来减少接收机中模拟数字转换器（DAC）的输入处的接收信号的可用动态范围的减小。在调制解调器的模拟前端（AFE）中提供了两个数模转换（D / A）转换。一个产生模拟信号进行传输。另一个产生用于在接收信号的模数（A / D）转换之前电子地消除回波的消除信号的模拟表示。优选实施例利用多路复用DAC架构通过在两个D / A转换的数据路径之间共享DAC电路来模拟两个DAC。

6. 发明授权

US06958723B1 Method and apparatus for reducing noise in analog-to-digital converter devices 有权
标题翻译：降低模数转换器装置噪声的方法和装置
公开(公告)号：US06958723B1
公开(公告)日：2005-10-25
申请号：US10803128
申请日：2004-03-17
申请人： Marco Corsi , William J. Bright , Martin Kithinji Kinyua , William David Smith
发明人： Marco Corsi , William J. Bright , Martin Kithinji Kinyua , William David Smith
IPC分类号： H03M1/08 , H03M1/38 , H03M1/44
CPC分类号： H03M1/08 , H03M1/447
摘要： An analog-to-digital converter apparatus has a plurality of stages. Each stage includes a residue amplifier having a first and second amplifier unit. Each of the amplifier units has a first input locus, a second input locus and an output locus. The amplifier units cooperate in receiving a differential input data signal at the first input loci. A DC level setting signal unit is coupled with the second input loci and provides a DC level setting current in a first current direction. A counter-current signal generating unit is coupled with the second input loci via a single coupling locus common with the second input loci and provides a control current signal to the second input loci in a second current direction opposite to the first current direction. The control current signal provides a DC level control for each of the amplifier units.
摘要翻译：模数转换器装置具有多个级。每个级包括具有第一和第二放大器单元的残余放大器。每个放大器单元具有第一输入轨迹，第二输入轨迹和输出轨迹。放大器单元合作在第一输入轨迹处接收差分输入数据信号。 DC电平设定信号单元与第二输入轨迹耦合，并且在第一电流方向上提供直流电平设定电流。逆流信号产生单元经由与第二输入轨迹共同的单个耦合轨迹与第二输入轨迹耦合，并且在与第一电流方向相反的第二电流方向上向第二输入轨迹提供控制电流信号。控制电流信号为每个放大器单元提供直流电平控制。

7. 发明授权

US06617886B2 Differential pair with high output signal crossover 有权
公开(公告)号：US06617886B2
公开(公告)日：2003-09-09
申请号：US10183255
申请日：2002-06-26
申请人： William J. Bright , Ranjit Gharpurey
发明人： William J. Bright , Ranjit Gharpurey
IPC分类号： H03K5153
CPC分类号： H03K5/08 , H03K5/2418
摘要： A buffer circuit includes a differential pair output switch having an additional NPN device and resistor operational to increase the common mode output voltage of the buffer during a switching event, such that the voltage movement at the common emitter node of the differential pair output switch for the buffer circuit is decreased to substantially reduce distortion of an output signal associated with a DAC that employs the buffer circuit.

8. 发明授权

US06583744B2 Correction circuit for beta mismatch between thermometer encoded and R-2R ladder segments of a current steering DAC 有权
标题翻译：校正电路，用于电流导向DAC的温度计编码和R-2R梯形段之间的β失配
公开(公告)号：US06583744B2
公开(公告)日：2003-06-24
申请号：US09887476
申请日：2001-06-22
申请人： William J. Bright
发明人： William J. Bright
IPC分类号： H03M168
CPC分类号： H03M1/0604 , H03M1/687 , H03M1/747 , H03M1/785
摘要： A current correction circuit 500 eliminates beta mismatches between a thermometer encoded segment 102 and a R-2R ladder segment 106 of a current steering digital-to-analog converter 100. The circuit 500 consists of three replica MSB unit current sources, I1, I2 and I3. The replica current I1 acts as a replica to a cascode device 206 of the MSB unit 200 of the current steering DAC 100. The replica current I2 replicates an effective base current equal to the total base current in the R-2R ladder circuit portion 300 of the current steering DAC 100. The replica current I3 replicates the total base current of the L output switches 310 in the LSB segment 106 of the current steering DAC 100. A high impedance summing node 506 produces a correction current ICOR=I1−(I2+I3). This current is equal to the current difference between an MSB unit 200 and the LSB segment 106. This correction current is then subtracted from the MSB unit current source 200 that supplies current into the R-2R ladder 300 such that the current supplied to the R-2R ladder 300 will be equal to the MSB replica current source minus the correction current.
摘要翻译：电流校正电路500消除了当前转向数模转换器100的温度计编码段102和R-2R梯形段106之间的β失配。电路500由三个复制MSB单元电流源I1，I2和 I3。复制电流I1用作当前转向DAC 100的MSB单元200的共源共栅器件206的副本。复制电流I2复制等于R-2R梯形电路部分300中的总基极电流的有效基极电流电流转向DAC 100.复制电流I3复制当前转向DAC 100的LSB段106中的L个输出开关310的总基极电流。高阻抗求和节点506产生校正电流ICOR = I1-（I2 + I3）。该电流等于MSB单元200和LSB段106之间的电流差。然后从向R-2R梯形图300提供电流的MSB单元电流源200中减去该校正电流，使得提供给R -2梯形图300将等于MSB复制电流源减去校正电流。

9. 发明授权

US08248289B2 Power and area efficient interleaved ADC 有权
标题翻译：电源和区域高效交错ADC
公开(公告)号：US08248289B2
公开(公告)日：2012-08-21
申请号：US12868539
申请日：2010-08-25
申请人： William J. Bright , Robert F. Payne
发明人： William J. Bright , Robert F. Payne
IPC分类号： H03M1/34
CPC分类号： H03M1/1215 , H03M1/1225 , H03M1/164 , H03M1/44
摘要： Pipeline analog-to-digital converters (ADCs) are commonly used for high frequency applications; however, operating at high sampling rates will often result in high power consumption or tight timing constraints. Here, though, an ADC is provided that allows for relaxed timing (which enables a high sampling rate) with low power consumption. This is accomplished through the use of multiplexed, front-end track-and-hold (T/H) circuits that sample on non-overlapping portions of a clocking signal in conjunction with “re-used” or shared analog processing circuitry.
摘要翻译：管道模数转换器（ADC）通常用于高频应用; 然而，以高采样率运行通常会导致高功耗或严格的时序限制。然而，在这里，提供了一种ADC，其具有低功耗的轻松定时（其实现高采样率）。这通过使用多路复用的前端跟踪保持（T / H）电路来实现，该电路在“重用”或共享的模拟处理电路的同时在时钟信号的非重叠部分上进行采样。

10. 发明授权

US06222478B1 Pipeline analog-to-digital conversion system using a modified coding scheme and method of operation 有权
标题翻译：管道模数转换系统采用修改后的编码方案和操作方法
公开(公告)号：US06222478B1
公开(公告)日：2001-04-24
申请号：US09298790
申请日：1999-04-23
申请人： William J. Bright
发明人： William J. Bright
IPC分类号： H03M134
CPC分类号： H03M1/168
摘要： A pipeline analog-to-digital conversion system (10) includes a plurality of cascaded subconverter stages (12) and a digital correction unit (16). Each subconverter stage (12) includes an n-bit analog-to-digital converter (26), an n-bit digital-to-analog converter (28), and an arithmetic unit (32). The n-bit analog-to-digital converter (26) generates a second intermediate digital signal (18) as a function of a first input analog signal (24) and a corresponding first intermediate digital signal (18) received from a previous stage (12).
摘要翻译：管道模数转换系统（10）包括多个级联子转换器级（12）和数字校正单元（16）。每个子转换器级（12）包括n位模数转换器（26），n位数模转换器（28）和运算单元（32）。 n位模数转换器（26）根据第一输入模拟信号（24）和从先前级接收的对应的第一中间数字信号（18）产生第二中间数字信号（18） 12）。

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