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1. 发明申请

US20120050081A1 POWER AND AREA EFFICIENT INTERLEAVED ADC 有权
标题翻译：功率和面积有效的交互式ADC
公开(公告)号：US20120050081A1
公开(公告)日：2012-03-01
申请号：US12868539
申请日：2010-08-25
申请人： William J. Bright , Robert F. Payne
发明人： William J. Bright , Robert F. Payne
IPC分类号： H03M1/00 , H03M1/12
CPC分类号： H03M1/1215 , H03M1/1225 , H03M1/164 , H03M1/44
摘要： Pipeline analog-to-digital converters (ADCs) are commonly used for high frequency applications; however, operating at high sampling rates will often result in high power consumption or tight timing constraints. Here, though, an ADC is provided that allows for relaxed timing (which enables a high sampling rate) with low power consumption. This is accomplished through the use of multiplexed, front-end track-and-hold (T/H) circuits that sample on non-overlapping portions of a clocking signal in conjunction with “re-used” or shared analog processing circuitry.
摘要翻译：管道模数转换器（ADC）通常用于高频应用; 然而，以高采样率运行通常会导致高功耗或严格的时序限制。然而，在这里，提供了一种ADC，其具有低功耗的轻松定时（其实现高采样率）。这通过使用多路复用的前端跟踪保持（T / H）电路来实现，该电路在“重用”或共享的模拟处理电路的同时在时钟信号的非重叠部分上进行采样。

2. 发明授权

US08248289B2 Power and area efficient interleaved ADC 有权
标题翻译：电源和区域高效交错ADC
公开(公告)号：US08248289B2
公开(公告)日：2012-08-21
申请号：US12868539
申请日：2010-08-25
申请人： William J. Bright , Robert F. Payne
发明人： William J. Bright , Robert F. Payne
IPC分类号： H03M1/34
CPC分类号： H03M1/1215 , H03M1/1225 , H03M1/164 , H03M1/44
摘要： Pipeline analog-to-digital converters (ADCs) are commonly used for high frequency applications; however, operating at high sampling rates will often result in high power consumption or tight timing constraints. Here, though, an ADC is provided that allows for relaxed timing (which enables a high sampling rate) with low power consumption. This is accomplished through the use of multiplexed, front-end track-and-hold (T/H) circuits that sample on non-overlapping portions of a clocking signal in conjunction with “re-used” or shared analog processing circuitry.
摘要翻译：管道模数转换器（ADC）通常用于高频应用; 然而，以高采样率运行通常会导致高功耗或严格的时序限制。然而，在这里，提供了一种ADC，其具有低功耗的轻松定时（其实现高采样率）。这通过使用多路复用的前端跟踪保持（T / H）电路来实现，该电路在“重用”或共享的模拟处理电路的同时在时钟信号的非重叠部分上进行采样。

3. 发明授权

US08958504B2 Carrier recovery in amplitude and phase modulated systems 有权
标题翻译：载波在幅度和相位调制系统中的恢复
公开(公告)号：US08958504B2
公开(公告)日：2015-02-17
申请号：US13607245
申请日：2012-09-07
申请人： Nirmal C. Warke , Robert F. Payne , Gerd Schuppener , Brad Kramer
发明人： Nirmal C. Warke , Robert F. Payne , Gerd Schuppener , Brad Kramer
IPC分类号： H03D3/18 , H03D3/24
CPC分类号： H04L27/0014 , H04L27/2273 , H04L27/3818 , H04L2027/0032 , H04L2027/0036 , H04L2027/0038 , H04L2027/0057 , H04L2027/0069
摘要： A method is provided. A multi-amplitude signal is received and downconverted so as to generate I and Q signals using a local oscillator signal. The I and Q signals are equalized, and the equalized I and Q signals are digitized. First and second gains are adjusted with the second and first digital signals, respectively, and applied to the equalized I and Q signals, respectively. The difference between the first and second amplified signals is determined, and an error signal is generated from the difference between the first and second amplified signals. The local oscillator signal is then adjusted with the error signal.
摘要翻译：提供了一种方法。多幅度信号被接收和下变频，以便使用本地振荡器信号产生I和Q信号。 I和Q信号被均衡，并且均衡的I和Q信号被数字化。第一和第二增益分别用第二和第一数字信号进行调整，分别应用于均衡的I和Q信号。确定第一和第二放大信号之间的差异，并且从第一和第二放大信号之间的差产生误差信号。然后用误差信号调整本机振荡器信号。

4. 发明授权

US08604838B2 Comparator with improved time constant 有权
标题翻译：比较器具有改进的时间常数
公开(公告)号：US08604838B2
公开(公告)日：2013-12-10
申请号：US13323540
申请日：2011-12-12
申请人： Robert F. Payne
发明人： Robert F. Payne
IPC分类号： H03K5/22
CPC分类号： H03K5/249 , H03K5/2481
摘要： An apparatus for comparing differential input signal inputs is provided. The apparatus comprises a CMOS sense amplifier (which has having a first input terminal, a second input terminal, a first output terminal, and a second output terminal), a first output circuit (which has a first load capacitance), a second output circuit (which has a second load capacitance), and an isolation circuit. The isolation circuit is coupled between the first output terminal of the CMOS sense amplifier and the first output circuit and is coupled between the second output terminal of the CMOS sense amplifier and the second output terminal of the CMOS sense amplifier. The isolation circuit isolates the first and second load capacitances from the CMOS sense amplifier.
摘要翻译：提供了一种用于比较差分输入信号输入的装置。该装置包括CMOS读出放大器（其具有第一输入端，第二输入端，第一输出端和第二输出端），第一输出电路（其具有第一负载电容），第二输出电路（其具有第二负载电容）和隔离电路。隔离电路耦合在CMOS读出放大器的第一输出端与第一输出电路之间，耦合在CMOS读出放大器的第二输出端和CMOS读出放大器的第二输出端之间。隔离电路将第一和第二负载电容与CMOS读出放大器隔离。

5. 发明申请

US20130101000A1 METHOD AND APPARATUS FOR PERFORMING SPECULATIVE DECISION FEEDBACK EQUALIZATION 有权
标题翻译：用于执行分布式决策反馈均衡的方法和装置
公开(公告)号：US20130101000A1
公开(公告)日：2013-04-25
申请号：US13278851
申请日：2011-10-21
申请人： Nirmal C. Warke , Robert F. Payne
发明人： Nirmal C. Warke , Robert F. Payne
IPC分类号： H04L27/01 , H04B1/38
CPC分类号： H04L25/03057 , H04L25/03343 , H04L25/14 , H04L27/01 , H04L2025/0349
摘要： A method for equalizing a received signal is provided. The signal is filtered and transmitted over a channel using an encoding scheme, where the encoding scheme has transmit symbols. This transmitted signal is then shaped such that the filtering and equalization adjust a set of taps in an equalization window so that the taps from the set are substantially equal to one another. Inter-symbol interference is then compensated for in the equalized signal using a speculative DFE with significantly reduced comparator levels.
摘要翻译：提供了一种用于均衡接收信号的方法。该信号被过滤并且使用编码方案通过信道发送，其中编码方案具有发送符号。该发射信号然后被成形为使得滤波和均衡调整均衡窗口中的一组抽头，使得来自该组的抽头基本上彼此相等。然后使用具有显着降低的比较器电平的推测性DFE在均衡信号中补偿符号间干扰。

6. 发明授权

US08305113B1 Intra-pair skew cancellation technique for differential signaling 有权
标题翻译：差分信号的对内偏移消除技术
公开(公告)号：US08305113B1
公开(公告)日：2012-11-06
申请号：US13100965
申请日：2011-05-04
申请人： Robert F. Payne
发明人： Robert F. Payne
IPC分类号： H03K5/153
CPC分类号： H03K5/003 , H04L25/0276
摘要： A method for deskewing a differential signal is provided. A common-mode voltage of a differential signal and an average for the common-mode voltage of the differential signal are measured. A difference between first and second portions of the differential signal is determined, and deskew information is derived from the common-mode voltage and the average. The deskew information can then be combined with the difference to deskew the differential signal.
摘要翻译：提供了一种用于偏差校正差分信号的方法。测量差分信号的共模电压和差分信号的共模电压的平均值。确定差分信号的第一和第二部分之间的差异，并且从共模电压和平均值导出偏斜消除信息。然后可以将偏斜消息信息与差异组合以对差分信号进行去偏移。

7. 发明申请

US20110121868A1 CLOCK BUFFER 有权
标题翻译：时钟缓冲
公开(公告)号：US20110121868A1
公开(公告)日：2011-05-26
申请号：US13017436
申请日：2011-01-31
申请人： Robert F. Payne , Marco Corsi , Tien-Ling Hsieh
发明人： Robert F. Payne , Marco Corsi , Tien-Ling Hsieh
IPC分类号： H03B1/00
CPC分类号： H03M1/002 , H03M1/1245
摘要： An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT differential pair having a third BJT and a fourth BJT, a first clamp having a fifth BJT and a sixth BJT, and a second clamp having a seventh BJT and an eighth BJT. The collector and base of the third BJT are respectively coupled to the collector and base of the first BJT, and the collector and base of the fourth BJT are respectively coupled to the collector and base of the second BJT. The bases of first, second, third, and fourth BJTs receive an input clock signal. The emitters of the fifth and sixth BJTs are coupled to the collectors of the first and third BJTs, while the emitters of the seventh and eight BJTs are coupled to the collectors of the second and fourth BJTs. The bases of the fifth and seventh BJT are adapted to receive a low clamping voltage, and the bases of the sixth and eighth BJTs are adapted to receive a high clamping voltage. Additionally, the first and second clamps is coupled to the collectors of the first, second, third, and fourth BJTs.
摘要翻译：提供了一种装置。该装置包括具有第一BJT和第二BJT的第一双极结型晶体管（BJT）差分对，具有第三BJT和第四BJT的第二BJT差分对，具有第五BJT和第六BJT的第一钳位，以及第二夹具具有第七BJT和第八BJT。第三BJT的集电极和基极分别耦合到第一BJT的集电极和基极，并且第四BJT的集电极和基极分别耦合到第二BJT的集电极和基极。第一，第二，第三和第四BJT的基极接收输入时钟信号。第五和第六BJT的发射器耦合到第一和第三BJT的集电极，而第七和第八BJT的发射极耦合到第二和第四BJT的集电极。第五和第七BJT的基极适于接收低钳位电压，并且第六和第八BJT的基极适于接收高钳位电压。另外，第一和第二夹具耦合到第一，第二，第三和第四BJT的收集器。

8. 发明申请

US20100214144A1 ERROR CORRECTION METHOD AND APPARATUS 有权
标题翻译：错误校正方法和装置
公开(公告)号：US20100214144A1
公开(公告)日：2010-08-26
申请号：US12393207
申请日：2009-02-26
申请人： Robert F. Payne , Marco Corsi
发明人： Robert F. Payne , Marco Corsi
IPC分类号： H03M1/12 , G05F1/10
CPC分类号： G05F3/265
摘要： A switched current source is provided. The switched current source is generally comprised of transistors and resistors, and the source has a high output impedance. Included with the switched current source is an error correction transistor and a resistor that cooperate to feed a current back through a bias transistor to correct an error that generally results from the current gains or β's of transistors within the switched current source. To accomplish this, however, the resistor is selected to have a value that is sufficiently large such that current from the error correction transistor flows back through the bias transistor.
摘要翻译：提供开关电流源。开关电流源通常由晶体管和电阻组成，源极具有高输出阻抗。与切换的电流源一起包括纠错晶体管和电阻器，其协作以通过偏置晶体管馈送电流以校正通常由开关电流源内的晶体管的电流增益或电流导致的误差。然而，为了实现这一点，电阻器被选择为具有足够大的值，使得来自误差校正晶体管的电流流过偏置晶体管。

9. 发明申请

US20100213986A1 CLOCK BUFFER 有权
标题翻译：时钟缓冲
公开(公告)号：US20100213986A1
公开(公告)日：2010-08-26
申请号：US12393188
申请日：2009-02-26
申请人： Robert F. Payne , Marco Corsi , Tien-Ling Hsieh
发明人： Robert F. Payne , Marco Corsi , Tien-Ling Hsieh
IPC分类号： H03B1/00
CPC分类号： H03M1/002 , H03M1/1245
摘要： An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT differential pair having a third BJT and a fourth BJT, a first clamp having a fifth BJT and a sixth BJT, and a second clamp having a seventh BJT and an eighth BJT. The collector and base of the third BJT are respectively coupled to the collector and base of the first BJT, and the collector and base of the fourth BJT are respectively coupled to the collector and base of the second BJT. The bases of first, second, third, and fourth BJTs receive an input clock signal. The emitters of the fifth and sixth BJTs are coupled to the collectors of the first and third BJTs, while the emitters of the seventh and eight BJTs are coupled to the collectors of the second and fourth BJTs. The bases of the fifth and seventh BJT are adapted to receive a low clamping voltage, and the bases of the sixth and eighth BJTs are adapted to receive a high clamping voltage. Additionally, the first and second clamps is coupled to the collectors of the first, second, third, and fourth BJTs.
摘要翻译：提供了一种装置。该装置包括具有第一BJT和第二BJT的第一双极结型晶体管（BJT）差分对，具有第三BJT和第四BJT的第二BJT差分对，具有第五BJT和第六BJT的第一钳位，以及第二夹具具有第七BJT和第八BJT。第三BJT的集电极和基极分别耦合到第一BJT的集电极和基极，并且第四BJT的集电极和基极分别耦合到第二BJT的集电极和基极。第一，第二，第三和第四BJT的基极接收输入时钟信号。第五和第六BJT的发射器耦合到第一和第三BJT的集电极，而第七和第八BJT的发射极耦合到第二和第四BJT的集电极。第五和第七BJT的基极适于接收低钳位电压，并且第六和第八BJT的基极适于接收高钳位电压。另外，第一和第二夹具耦合到第一，第二，第三和第四BJT的收集器。

10. 发明授权

US07474126B2 Parallel bipolar logic devices and methods for using such 有权
标题翻译：并联双极逻辑器件及其使用方法
公开(公告)号：US07474126B2
公开(公告)日：2009-01-06
申请号：US11626871
申请日：2007-01-25
申请人： Robert F. Payne
发明人： Robert F. Payne
IPC分类号： H03K19/20 , H03K19/086
CPC分类号： H03K19/20
摘要： Various logic gates and methods for using such are disclosed herein. For example, some embodiments of the present invention provide parallel differential logic gates. Such logic gates include two or more differential input pairs. The collectors of the first transistors in each of the differential pairs are all electrically coupled to an upper voltage via a first load resistor. Similarly, the collectors of the second transistors in each of the differential pairs are all electrically coupled to an upper voltage via a second load resistor. Depending upon the relative values selected for the first and second load resistors, the gate operates as an AND gate or an OR gate.
摘要翻译：本文公开了各种逻辑门及其使用方法。例如，本发明的一些实施例提供并行差分逻辑门。这种逻辑门包括两个或更多个差分输入对。每个差分对中的第一晶体管的集电极都经由第一负载电阻器电耦合到上电压。类似地，每个差分对中的第二晶体管的集电极都经由第二负载电阻器电耦合到高电压。根据为第一和第二负载电阻选择的相对值，门作为“与”门或“或”门。

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