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1. 发明公开

CN1669224A 开关电流模数转换器失效转让
公开(公告)号：CN1669224A
公开(公告)日：2005-09-14
申请号：CN03816886.3
申请日：2003-07-08
申请人：皇家飞利浦电子股份有限公司
发明人： J·B·休斯
IPC分类号： H03M1/14
CPC分类号： H03M1/0695 , H03M1/447
摘要：一种电流模式模数转换器使用一种利用双相时钟来工作并且要求输入信号只在一个相位期间出现的转换级。采样保持电路(120，130，135)在第一时钟相位期间对输入信号采样，在第二时钟相位期间，通过无反冲比较器电路(140)从被保持的输入电流的镜像电流产生量化的位值。在第二时钟相位期间，还利用量化的值和保持的输入电流的非镜像形式产生残余电流。作为选择，两个比较器电路(140，140″)可用来提供两级量化，使电流反射镜引入的误差能够被冗余带符号的数字算法来校正。两条转换级流水线(Si′，Si″)能多路复用以使转换速度加倍。

2. 发明授权

CN100423451C 开关电流模数转换器失效转让
公开(公告)号：CN100423451C
公开(公告)日：2008-10-01
申请号：CN03816886.3
申请日：2003-07-08
申请人： NXP股份有限公司
发明人： J·B·休斯
IPC分类号： H03M1/14
CPC分类号： H03M1/0695 , H03M1/447
摘要：一种电流模式模数转换器使用一种利用双相时钟来工作并且要求输入信号只在一个相位期间出现的转换级。采样保持电路(120，130，135)在第一时钟相位期间对输入信号采样，在第二时钟相位期间，通过无反冲比较器电路(140)从被保持的输入电流的镜像电流产生量化的位值。在第二时钟相位期间，还利用量化的值和保持的输入电流的非镜像形式产生残余电流。作为选择，两个比较器电路(140，140″)可用来提供两级量化，使电流反射镜引入的误差能够被冗余带符号的数字算法来校正。两条转换级流水线(Si′，Si″)能多路复用以使转换速度加倍。

3. 发明公开

EP2055006A1 ANALOG-TO-DIGITAL CONVERSION USING ASYNCHRONOUS CURRENT-MODE CYCLIC COMPARISON 有权
标题翻译：模数转换采用异步循环动力模式相比
公开(公告)号：EP2055006A1
公开(公告)日：2009-05-06
申请号：EP07764097.7
申请日：2007-07-20
申请人： Intellectual Ventures Fund 27 LLC
发明人： KOK, Chi Wah , TAM, Wing Shan
IPC分类号： H03M1/44
CPC分类号： H03M1/125 , H03M1/447
摘要： An asynchronous cyclic current-mode analog-to-digital converter (ADC) is disclosed. The ADC comprises a plurality of sub-ADCs cascading from the first stage to the last stage, each sub-ADC comprising a current-mode ADC having a digital output, an analog current input, a reference current input and an analog current output. The analog current input of each stage, except the first stage, is operatively connected to the analog current output of the immediately preceding stage. The plurality of sub-ADCs are configured to operate without synchronization with each other.

4. 发明公开

EP1046231A2 ANALOGUE TO DIGITAL CONVERTER 有权
标题翻译：模拟数字转换器
公开(公告)号：EP1046231A2
公开(公告)日：2000-10-25
申请号：EP99947472.9
申请日：1999-09-23
申请人： Koninklijke Philips Electronics N.V.
发明人： HUGHES, John, B. , REDMAN-WHITE, William , BRACEY, Mark
IPC分类号： H03M3/00
CPC分类号： H03M1/0682 , H03M1/1215 , H03M1/1225 , H03M1/145 , H03M1/447
摘要： (57) Abstract A current mode pipelined analogue to digital converter (ADC) has a plurality of serially connected conversion stages. Each conversion stage has an input (40) for receiving a sampled and held current which is connected via a switch (S41) to a first current memory (M42) and via a switch (S40) to a second current memory (M41). The output of the second current memory (M41) is fed via a switch (S44) to one input of a summing junction (48). The output of the first current memory (M42) is fed via a switch (S42) to the input of a comparator (C43) whose output is clocked into a latch (L44) whose Q output is connected to an output (45) as the digital result of the conversion. The Q output of the latch (L44) is also connected to a digital to analogue converter (46) whose analogue output is fed to a second input of the summing junction (48) via a switch (S43) to form the analogue residue signal for application via output (47) to the next conversion stage in the pipeline. The stage has the advantage that the analogue signal is fed from stage to stage using only one current memory (M41) thus reducing transmission loss and that corruption of the analogue signal by comparator 'kick back' is avoided by using a further current memory (M42) in parallel with the signal path current memory (M41).

5. 发明申请

WO2004010586A2 SWITCHED-CURRENT ANALOGUE-TO-DIGITAL CONVERTER 审中-公开
标题翻译：开关电流模拟数字转换器
公开(公告)号：WO2004010586A2
公开(公告)日：2004-01-29
申请号：PCT/IB0303027
申请日：2003-07-08
申请人： KONINKL PHILIPS ELECTRONICS NV , HUGHES JOHN B
发明人： HUGHES JOHN B
IPC分类号： H03M1/44 , H03M1/06 , H03M1/00
CPC分类号： H03M1/0695 , H03M1/447
摘要： A current mode analogue-to-digital converter uses a conversion stage which operates using a two-phase clock and which requires the input signal to be present during only one of the phases. A sample-and-hold circuit (120, 130, 135) samples the input signal during the first clock phase and during the second clock phase a quantised bit value is generated from a mirror of the held input current by a kickback-free comparator circuit (140). Also during the second clock phase a residue is generated using the quantised value and a non-mirrored version of the held input current. Optionally, two comparator circuits (140, 140") may be used to provide two-level quantisation, enabling errors introduced by the current mirror to be corrected by a Redundant Signed Digit algorithm. Two pipelines of conversion stages (S
摘要翻译：电流模式模拟 - 数字转换器使用转换级，其使用两相时钟进行操作，并且需要在仅一个相位期间存在输入信号。采样和保持电路（120,130,135）在第一时钟相位期间对输入信号进行采样，并且在第二时钟相位期间，通过无反冲比较器电路从保持的输入电流的反射镜产生量化位值（140）。同样在第二时钟阶段期间，使用量化值和保持的输入电流的非镜像版本来生成残差。可选地，可以使用两个比较器电路（140,140“）来提供两级量化，使得由电流镜引入的误差能够通过冗余有符号数字算法来校正。转换级的两条管线（S

6. 发明申请

WO2008014676A1 ANALOG-TO-DIGITAL CONVERSION USING ASYNCHRONOUS CURRENT-MODE CYCLIC COMPARISON 审中-公开
标题翻译：使用异步电流模式循环比较的模拟到数字转换
公开(公告)号：WO2008014676A1
公开(公告)日：2008-02-07
申请号：PCT/CN2007/002213
申请日：2007-07-20
申请人： THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY , KOK, Chi Wah , TAM, Wing Shan
发明人： KOK, Chi Wah , TAM, Wing Shan
IPC分类号： H03M1/44
CPC分类号： H03M1/125 , H03M1/447
摘要： An asynchronous cyclic current-mode analog-to-digital converter (ADC) is disclosed. The ADC comprises a plurality of sub-ADCs cascading from the first stage to the last stage, each sub-ADC comprising a current-mode ADC having a digital output, an analog current input, a reference current input and an analog current output. The analog current input of each stage, except the first stage, is operatively connected to the analog current output of the immediately preceding stage. The plurality of sub-ADCs are configured to operate without synchronization with each other.
摘要翻译：公开了一种异步循环电流模式模数转换器（ADC）。 ADC包括从第一级到最后级级联的多个子ADC，每个子ADC包括具有数字输出的电流模式ADC，模拟电流输入，参考电流输入和模拟电流输出。除了第一级之外，每级的模拟电流输入可操作地连接到紧前一级的模拟电流输出。多个子ADC被配置为彼此不同步地操作。

7. 发明授权

EP2055006B1 ANALOG-TO-DIGITAL CONVERSION USING ASYNCHRONOUS CURRENT-MODE CYCLIC COMPARISON 有权
标题翻译：模数转换采用异步循环动力模式相比
公开(公告)号：EP2055006B1
公开(公告)日：2012-04-11
申请号：EP07764097.7
申请日：2007-07-20
申请人： Intellectual Ventures Fund 27 LLC
发明人： KOK, Chi Wah , TAM, Wing Shan
IPC分类号： H03M1/12 , H03M1/44
CPC分类号： H03M1/125 , H03M1/447
摘要： An asynchronous cyclic current-mode analog-to-digital converter (ADC) is disclosed. The ADC comprises a plurality of sub-ADCs cascading from the first stage to the last stage, each sub-ADC comprising a current-mode ADC having a digital output, an analog current input, a reference current input and an analog current output. The analog current input of each stage, except the first stage, is operatively connected to the analog current output of the immediately preceding stage. The plurality of sub-ADCs are configured to operate without synchronization with each other.

8. 发明公开

EP1552614A2 SWITCHED-CURRENT ANALOGUE-TO-DIGITAL CONVERTER 有权
标题翻译：开关电流模拟数字转换器
公开(公告)号：EP1552614A2
公开(公告)日：2005-07-13
申请号：EP03740936.4
申请日：2003-07-08
申请人： Koninklijke Philips Electronics N.V.
发明人： HUGHES, John B.,c/o Philips Intellectual Property
IPC分类号： H03M1/00
CPC分类号： H03M1/0695 , H03M1/447
摘要： A current mode analogue-to-digital converter uses a conversion stage which operates using a two-phase clock and which requires the input signal to be present during only one of the phases. A sample-and-hold circuit (120, 130, 135) samples the input signal during the first clock phase and during the second clock phase a quantised bit value is generated from a mirror of the held input current by a kickback-free comparator circuit (140). Also during the second clock phase a residue is generated using the quantised value and a non-mirrored version of the held input current. Optionally, two comparator circuits (140, 140') may be used to provide two-level quantisation, enabling errors introduced by the current mirror to be corrected by a Redundant Signed Digit algorithm. Two pipelines of conversion stages (Si’, Si”) can be multiplexed to double the conversion rate.
摘要翻译：电流模式模数转换器使用转换级，该转换级使用两相时钟进行操作，并且仅在其中一个相位期间要求输入信号存在。采样和保持电路（120,130,135）在第一时钟相位期间对输入信号进行采样，并且在第二时钟相位期间，通过无反冲比较器电路从保持的输入电流的镜像中产生量化比特值（140）。同样在第二时钟阶段期间，使用量化值和保持的输入电流的非镜像版本来生成余量。可选地，可以使用两个比较器电路（140,140'）来提供两级量化，使得能够通过冗余签名数字算法校正由电流镜引起的误差。两个转换级管线（Si'，Si“）可以被复用以使转换速率加倍。

9. 发明授权

EP1046231B1 ANALOGUE TO DIGITAL CONVERTER 有权
标题翻译：模拟数字转换器
公开(公告)号：EP1046231B1
公开(公告)日：2004-04-14
申请号：EP99947472.9
申请日：1999-09-23
申请人： Koninklijke Philips Electronics N.V.
发明人： HUGHES, John, B. , REDMAN-WHITE, William , BRACEY, Mark
IPC分类号： H03M3/00
CPC分类号： H03M1/0682 , H03M1/1215 , H03M1/1225 , H03M1/145 , H03M1/447
摘要： (57) Abstract A current mode pipelined analogue to digital converter (ADC) has a plurality of serially connected conversion stages. Each conversion stage has an input (40) for receiving a sampled and held current which is connected via a switch (S41) to a first current memory (M42) and via a switch (S40) to a second current memory (M41). The output of the second current memory (M41) is fed via a switch (S44) to one input of a summing junction (48). The output of the first current memory (M42) is fed via a switch (S42) to the input of a comparator (C43) whose output is clocked into a latch (L44) whose Q output is connected to an output (45) as the digital result of the conversion. The Q output of the latch (L44) is also connected to a digital to analogue converter (46) whose analogue output is fed to a second input of the summing junction (48) via a switch (S43) to form the analogue residue signal for application via output (47) to the next conversion stage in the pipeline. The stage has the advantage that the analogue signal is fed from stage to stage using only one current memory (M41) thus reducing transmission loss and that corruption of the analogue signal by comparator "kick back" is avoided by using a further current memory (M42) in parallel with the signal path current memory (M41).

10. 发明授权

EP1739842B1 A/D converter 有权
标题翻译： A / D转换器
公开(公告)号：EP1739842B1
公开(公告)日：2009-01-14
申请号：EP05023220.6
申请日：2005-10-25
申请人： Fujitsu Microelectronics Limited
发明人： Suzuki, Hisao Fujitsu VLSI Limited
IPC分类号： H03M1/44
CPC分类号： H03M1/447

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