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1. 发明申请

US20050221571A1 Dual metal schottky diode 有权
标题翻译：双金属肖特基二极管
公开(公告)号：US20050221571A1
公开(公告)日：2005-10-06
申请号：US10814673
申请日：2004-03-30
申请人： Richard Irwin , Tony Phan , Hong-Ryong Kim , Ming-Yeh Chuang , Jennifer Dumin , Patrick Jones , Fredric Bailey
发明人： Richard Irwin , Tony Phan , Hong-Ryong Kim , Ming-Yeh Chuang , Jennifer Dumin , Patrick Jones , Fredric Bailey
IPC分类号： H01L21/20 , H01L21/329 , H01L29/47 , H01L29/80 , H01L29/872 , H01L29/93 , H01L31/112
CPC分类号： H01L29/66143 , H01L29/47 , H01L29/872
摘要： An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another embodiment of the invention is a method of manufacturing a Schottky diode 22 that includes providing a semiconductor substrate 3, forming a barrier layer 26 over the semiconductor substrate 3, forming a first metal layer 23 over the semiconductor substrate 3, annealing the semiconductor substrate 3 to form areas 24 of reacted first metal and areas 23 of un-reacted first metal, and removing selected areas 23 of the un-reacted first metal. The method further includes forming a second metal layer 30 over the semiconductor substrate 3 and annealing the semiconductor substrate 3 to form areas 28 of reacted second metal and areas 30 of un-reacted second metal
摘要翻译：本发明的实施例是具有半导体衬底3，第一金属24，阻挡层26和第二金属28的肖特基二极管22。本发明的另一实施例是制造肖特基二极管22的方法，其包括提供半导体衬底3，在半导体衬底3上形成阻挡层26，在半导体衬底3上方形成第一金属层23，退火半导体衬底3 以形成反应的第一金属的区域24和未反应的第一金属的区域23，并且去除未反应的第一金属的选定区域23。该方法还包括在半导体衬底3上形成第二金属层30并退火半导体衬底3以形成反应的第二金属的区域28和未反应的第二金属的区域30

2. 发明申请

US20050218433A1 Dual metal schottky diode 有权
标题翻译：双金属肖特基二极管
公开(公告)号：US20050218433A1
公开(公告)日：2005-10-06
申请号：US11095245
申请日：2005-03-30
申请人： Richard Irwin , Tony Phan , Hong-Ryong Kim , Ming-Yeh Chuang , Jennifer Dumin , Patrick Jones
发明人： Richard Irwin , Tony Phan , Hong-Ryong Kim , Ming-Yeh Chuang , Jennifer Dumin , Patrick Jones
IPC分类号： H01L21/20 , H01L21/329 , H01L29/47 , H01L29/80 , H01L29/872 , H01L29/93 , H01L31/112
CPC分类号： H01L29/66143 , H01L29/47 , H01L29/872
摘要： An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another embodiment of the invention is a method of manufacturing a Schottky diode 22 that includes providing a semiconductor substrate 3, forming a barrier layer 26 over the semiconductor substrate 3, forming a first metal layer 23 over the semiconductor substrate 3, annealing the semiconductor substrate 3 to form areas 24 of reacted first metal and areas 23 of un-reacted first metal, and removing selected areas 23 of the un-reacted first metal. The method further includes forming a second metal layer 30 over the semiconductor substrate 3 and annealing the semiconductor substrate 3 to form areas 28 of reacted second metal and areas 30 of un-reacted second metal.
摘要翻译：本发明的实施例是具有半导体衬底3，第一金属24，阻挡层26和第二金属28的肖特基二极管22。本发明的另一实施例是制造肖特基二极管22的方法，其包括提供半导体衬底3，在半导体衬底3上形成阻挡层26，在半导体衬底3上形成第一金属层23，对半导体衬底3退火以形成反应的第一金属的区域24和未反应的第一金属的区域23，并且去除未反应的第一金属的选定区域23。该方法还包括在半导体衬底3上形成第二金属层30并退火半导体衬底3以形成反应的第二金属的区域28和未反应的第二金属的区域30。

3. 发明授权

US07902055B2 Method of manufacturing a dual metal Schottky diode 有权
标题翻译：制造双金属肖特基二极管的方法
公开(公告)号：US07902055B2
公开(公告)日：2011-03-08
申请号：US11095245
申请日：2005-03-30
申请人： Richard B. Irwin , Tony T. Phan , Hong-Ryong Kim , Ming-Yeh Chuang , Jennifer S. Dumin , Patrick J. Jones , Fredric D. Bailey
发明人： Richard B. Irwin , Tony T. Phan , Hong-Ryong Kim , Ming-Yeh Chuang , Jennifer S. Dumin , Patrick J. Jones , Fredric D. Bailey
IPC分类号： H01L29/872 , H01L29/47
CPC分类号： H01L29/66143 , H01L29/47 , H01L29/872
摘要： An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another embodiment of the invention is a method of manufacturing a Schottky diode 22 that includes providing a semiconductor substrate 3, forming a barrier layer 26 over the semiconductor substrate 3, forming a first metal layer 23 over the semiconductor substrate 3, annealing the semiconductor substrate 3 to form areas 24 of reacted first metal and areas 23 of un-reacted first metal, and removing selected areas 23 of the un-reacted first metal. The method further includes forming a second metal layer 30 over the semiconductor substrate 3 and annealing the semiconductor substrate 3 to form areas 28 of reacted second metal and areas 30 of un-reacted second metal.
摘要翻译：本发明的一个实施例是具有半导体衬底3，第一金属24，势垒层26和第二金属28的肖特基二极管22.本发明的另一实施例是制造肖特基二极管22的方法，其包括提供半导体衬底3，在半导体衬底3上形成阻挡层26，在半导体衬底3上形成第一金属层23，退火半导体衬底3，形成反应的第一金属的区域24和未反应的第一金属的区域23;以及去除未反应的第一金属的选定区域23。该方法还包括在半导体衬底3上形成第二金属层30并退火半导体衬底3以形成反应的第二金属的区域28和未反应的第二金属的区域30。

4. 发明授权

US06972470B2 Dual metal Schottky diode 有权
标题翻译：双金属肖特基二极管
公开(公告)号：US06972470B2
公开(公告)日：2005-12-06
申请号：US10814673
申请日：2004-03-30
申请人： Richard B. Irwin , Tony T. Phan , Hong-Ryong Kim , Ming-Yeh Chuang , Jennifer S. Dumin , Patrick J. Jones , Fredric D. Bailey
发明人： Richard B. Irwin , Tony T. Phan , Hong-Ryong Kim , Ming-Yeh Chuang , Jennifer S. Dumin , Patrick J. Jones , Fredric D. Bailey
IPC分类号： H01L21/20 , H01L21/329 , H01L29/47 , H01L29/80 , H01L29/872 , H01L29/93 , H01L31/112 , H01L27/95
CPC分类号： H01L29/66143 , H01L29/47 , H01L29/872
摘要： An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another embodiment of the invention is a method of manufacturing a Schottky diode 22 that includes providing a semiconductor substrate 3, forming a barrier layer 26 over the semiconductor substrate 3, forming a first metal layer 23 over the semiconductor substrate 3, annealing the semiconductor substrate 3 to form areas 24 of reacted first metal and areas 23 of un-reacted first metal, and removing selected areas 23 of the un-reacted first metal. The method further includes forming a second metal layer 30 over the semiconductor substrate 3 and annealing the semiconductor substrate 3 to form areas 28 of reacted second metal and areas 30 of un-reacted second metal.
摘要翻译：本发明的实施例是具有半导体衬底3，第一金属24，阻挡层26和第二金属28的肖特基二极管22。本发明的另一实施例是制造肖特基二极管22的方法，其包括提供半导体衬底3，在半导体衬底3上形成阻挡层26，在半导体衬底3上方形成第一金属层23，退火半导体衬底3 以形成反应的第一金属的区域24和未反应的第一金属的区域23，并且去除未反应的第一金属的选定区域23。该方法还包括在半导体衬底3上形成第二金属层30并退火半导体衬底3以形成反应的第二金属的区域28和未反应的第二金属的区域30。

5. 发明授权

US08455950B2 ESD diode with PSD partially overlying P-Epi circumferential of PSD 有权
标题翻译：具有PSD的ESD二极管部分覆盖PSD的P-Epi圆周
公开(公告)号：US08455950B2
公开(公告)日：2013-06-04
申请号：US13094955
申请日：2011-04-27
申请人： Ming-Yeh Chuang
发明人： Ming-Yeh Chuang
IPC分类号： H01L27/02
CPC分类号： H01L21/22 , H01L21/265 , H01L27/0255 , H01L29/0615 , H01L29/0692 , H01L29/8611
摘要： An integrated circuit structure includes a semiconductor doped area (NWell) having a first conductivity type, and a layer (PSD) that overlies a portion of said doped area (NWell) and has a doping of an opposite second type of conductivity that is opposite from the first conductivity type of said doped area (NWell), and said layer (PSD) having a corner in cross-section, and the doping of said doped area (NWell) forming a junction beneath said layer (PSD) with the doping of said doped area (NWell) diluted in a vicinity below the corner of said layer (PSD). Other integrated circuits, substructures, devices, processes of manufacturing, and processes of testing are also disclosed.
摘要翻译：集成电路结构包括具有第一导电类型的半导体掺杂区域（NWell）和覆盖所述掺杂区域（NWell）的一部分的层（PSD），并且具有与第二导电类型相反的第二类型的导电性的掺杂所述掺杂区域（NWell）的第一导电类型和具有横截面角的所述层（PSD），以及在所述层（PSD）下面形成结的所述掺杂区域（NWell）的掺杂，在所述层（PSD）的角下方附近稀释的掺杂区域（NWell）。还公开了其它集成电路，子结构，器件，制造工艺和测试过程。

6. 发明授权

US08772103B2 Low temperature implant scheme to improve BJT current gain 有权
标题翻译：低温注入方案，提高BJT电流增益
公开(公告)号：US08772103B2
公开(公告)日：2014-07-08
申请号：US13246362
申请日：2011-09-27
申请人： Ming-Yeh Chuang
发明人： Ming-Yeh Chuang
IPC分类号： H01L21/8249
CPC分类号： H01L21/26593 , H01L21/8249 , H01L27/0623 , H01L29/66272
摘要： A process of forming an integrated circuit containing an npn BJT and an NMOS transistor by cooling the integrated circuit substrate to 5° C. or colder and concurrently implanting n-type dopants, at a specified minimum dose according to species, into the emitter region of the BJT and the source and drain regions of the NMOS transistor. A process of forming an integrated circuit containing a pnp BJT and a PMOS transistor by cooling the integrated circuit substrate to 5° C. or colder and concurrently implanting p-type dopants, at a specified minimum dose according to species, into the emitter region of the BJT and the source and drain regions of the PMOS transistor. A process of forming an integrated circuit containing an implant region by cooling the integrated circuit substrate to 5° C. or colder and implanting atoms, at a specified minimum dose according to species, into the implant region.
摘要翻译：通过将集成电路基板冷却至5℃，形成包含npn BJT和NMOS晶体管的集成电路的工艺，或者根据物种以特定的最小剂量将n型掺杂剂更冷或同时地注入到发射极区域 BJT以及NMOS晶体管的源极和漏极区域。通过将集成电路基板冷却至5℃，或者将根据物种的规定的最小剂量同时植入p型掺杂剂，形成包含pnp BJT和PMOS晶体管的集成电路的工艺， BJT以及PMOS晶体管的源极和漏极区域。通过将集成电路基板冷却至5℃或更冷的方式形成包含注入区域的集成电路的过程，并且根据种类以特定的最小剂量将原子注入到植入区域中。

7. 发明申请

US20130065374A1 Fluorine Implant Under Isolation Dielectric Structures to Improve Bipolar Transistor Performance and Matching 有权
标题翻译：氟植入物隔离电介质结构提高双极晶体管性能和匹配
公开(公告)号：US20130065374A1
公开(公告)日：2013-03-14
申请号：US13451355
申请日：2012-04-19
申请人： Weidong Tian , Ming-Yeh Chuang , Rajni J. Aggarwal
发明人： Weidong Tian , Ming-Yeh Chuang , Rajni J. Aggarwal
IPC分类号： H01L21/331
CPC分类号： H01L29/732 , H01L29/1004 , H01L29/66272
摘要： A method of fabricating an integrated circuit including bipolar transistors that reduces the effects of transistor performance degradation and transistor mismatch caused by charging during plasma etch, and the integrated circuit so formed. A fluorine implant is performed at those locations at which isolation dielectric structures between base and emitter are to be formed, prior to formation of the isolation dielectric. The isolation dielectric structures may be formed by either shallow trench isolation, in which the fluorine implant is performed after trench etch, or LOCOS oxidation, in which the fluorine implant is performed prior to thermal oxidation. The fluorine implant may be normal to the device surface or at an angle from the normal. Completion of the integrated circuit is then carried out, including the use of relatively thick copper metallization requiring plasma etch.
摘要翻译：一种制造包括双极晶体管的集成电路的方法，其降低了等离子体蚀刻期间由充电引起的晶体管性能下降和晶体管失配的影响，以及如此形成的集成电路。在形成隔离电介质之前，在要形成基极和发射极之间的隔离电介质结构的那些位置处进行氟注入。隔离电介质结构可以通过浅沟槽隔离来形成，其中氟注入在沟槽蚀刻之后进行，或LOCOS氧化，其中氟注入在热氧化之前进行。氟注入可以垂直于器件表面或与法线成一定角度。然后执行集成电路的完成，包括使用需要等离子体蚀刻的相对厚的铜金属化。

8. 发明申请

US20110298092A1 DIODES WITH A DOG BONE OR CAP-SHAPED JUNCTION PROFILE TO ENHANCE ESD PERFORMANCE, AND OTHER SUBSTRUCTURES, INTEGRATED CIRCUITS AND PROCESSES OF MANUFACTURE AND TESTING 有权
标题翻译：具有DOG骨头或CAP形状连接轮廓的二极管，以增强ESD性能和其他结构，集成电路和制造和测试过程
公开(公告)号：US20110298092A1
公开(公告)日：2011-12-08
申请号：US13094955
申请日：2011-04-27
申请人： Ming-Yeh Chuang
发明人： Ming-Yeh Chuang
IPC分类号： H01L29/06 , H01L21/265 , H01L21/22
CPC分类号： H01L21/22 , H01L21/265 , H01L27/0255 , H01L29/0615 , H01L29/0692 , H01L29/8611
摘要： An integrated circuit structure includes a semiconductor doped area (NWell) having a first conductivity type, and a layer (PSD) that overlies a portion of said doped area (NWell) and has a doping of an opposite second type of conductivity that is opposite from the first conductivity type of said doped area (NWell), and said layer (PSD) having a corner in cross-section, and the doping of said doped area (NWell) forming a junction beneath said layer (PSD) with the doping of said doped area (NWell) diluted in a vicinity below the corner of said layer (PSD). Other integrated circuits, substructures, devices, processes of manufacturing, and processes of testing are also disclosed.
摘要翻译：集成电路结构包括具有第一导电类型的半导体掺杂区域（NWell）和覆盖所述掺杂区域（NWell）的一部分的层（PSD），并且具有与第二导电类型相反的第二类型的导电性的掺杂所述掺杂区域（NWell）的第一导电类型和具有横截面角的所述层（PSD），以及在所述层（PSD）下面形成结的所述掺杂区域（NWell）的掺杂，在所述层（PSD）的角下方附近稀释的掺杂区域（NWell）。还公开了其它集成电路，子结构，器件，制造工艺和测试过程。

9. 发明申请

US20050040489A1 Diode having a double implanted guard ring 有权
标题翻译：二极管具有双植入保护环
公开(公告)号：US20050040489A1
公开(公告)日：2005-02-24
申请号：US10644536
申请日：2003-08-20
申请人： Ming-Yeh Chuang , William Loftin , Scott Montgomery
发明人： Ming-Yeh Chuang , William Loftin , Scott Montgomery
IPC分类号： H01L27/06 , H01L27/08 , H01L29/872 , H01L27/095
CPC分类号： H01L27/0629 , H01L27/0814 , H01L29/872 , Y10S438/983
摘要： The present invention provides a diode 200 that includes a substrate 215 doped with a first type dopant and a double implanted guard ring 245 located within the substrate and doped with a second type dopant opposite the first type dopant and having a first doped profile region 245a and a second doped profile region 245b. The present invention also includes a method of manufacturing this diode and an integrated circuit that utilizes this diode 200 within a CMOS and bipolar transistor integrated circuit 600.
摘要翻译：本发明提供一种二极管200，其包括掺杂有第一类型掺杂剂的衬底215和位于衬底内的双注入保护环245，并掺杂有与第一类型掺杂剂相反的第二类型掺杂剂，并且具有第一掺杂分布区域245a和第二掺杂分布区域245b。本发明还包括制造该二极管的方法和在CMOS和双极晶体管集成电路600内利用该二极管200的集成电路。

10. 发明授权

US08609501B2 Fluorine implant under isolation dielectric structures to improve bipolar transistor performance and matching 有权
标题翻译：隔离介质结构中的氟植入物，以改善双极晶体管的性能和匹配
公开(公告)号：US08609501B2
公开(公告)日：2013-12-17
申请号：US13451355
申请日：2012-04-19
申请人： Weidong Tian , Ming-Yeh Chuang , Rajni J. Aggarwal
发明人： Weidong Tian , Ming-Yeh Chuang , Rajni J. Aggarwal
IPC分类号： H01L21/331
CPC分类号： H01L29/732 , H01L29/1004 , H01L29/66272
摘要： A method of fabricating an integrated circuit including bipolar transistors that reduces the effects of transistor performance degradation and transistor mismatch caused by charging during plasma etch, and the integrated circuit so formed. A fluorine implant is performed at those locations at which isolation dielectric structures between base and emitter are to be formed, prior to formation of the isolation dielectric. The isolation dielectric structures may be formed by either shallow trench isolation, in which the fluorine implant is performed after trench etch, or LOCOS oxidation, in which the fluorine implant is performed prior to thermal oxidation. The fluorine implant may be normal to the device surface or at an angle from the normal. Completion of the integrated circuit is then carried out, including the use of relatively thick copper metallization requiring plasma etch.
摘要翻译：一种制造包括双极晶体管的集成电路的方法，其降低了等离子体蚀刻期间由充电引起的晶体管性能下降和晶体管失配的影响，以及如此形成的集成电路。在形成隔离电介质之前，在要形成基极和发射极之间的隔离电介质结构的那些位置处进行氟注入。隔离电介质结构可以通过浅沟槽隔离来形成，其中氟注入在沟槽蚀刻之后进行，或LOCOS氧化，其中氟注入在热氧化之前进行。氟注入可以垂直于器件表面或与法线成一定角度。然后执行集成电路的完成，包括使用需要等离子体蚀刻的相对厚的铜金属化。

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