专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06331735B1 Method to improve chip scale package electrostatic discharge performance and suppress marking artifacts 有权
公开(公告)号：US06331735B1
公开(公告)日：2001-12-18
申请号：US09161062
申请日：1998-09-25
申请人： Richard C. Blish, II , Colin Hatchard , Ian Morgan
发明人： Richard C. Blish, II , Colin Hatchard , Ian Morgan
IPC分类号： H01L2348
CPC分类号： H01L23/3114 , H01L23/544 , H01L23/60 , H01L24/48 , H01L2223/54473 , H01L2224/05599 , H01L2224/48091 , H01L2224/4824 , H01L2224/85399 , H01L2924/00013 , H01L2924/00014 , H01L2924/01019 , H01L2924/01077 , H01L2924/10253 , H01L2924/12042 , H01L2224/29099 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： The present invention is a method for providing chip scale package. The method of the present invention includes providing a die with a first side, a second side, and a plurality of edges; applying a substance which protects against electrostatic discharge to the first side of the die and to the plurality of edges; and providing components on the second side of the die. The method of the present invention protects the chip scale package from electrostatic discharges. Markings may also be placed on the substance without damaging the chip in the package.

2. 发明授权

US06495393B2 Method to improve chip scale package electrostatic discharge performance and suppress marking artifacts 失效
标题翻译：提高芯片级封装静电放电性能并抑制标记伪影的方法
公开(公告)号：US06495393B2
公开(公告)日：2002-12-17
申请号：US09836747
申请日：2001-04-17
申请人： Richard C. Blish, II , Colin Hatchard , Ian Morgan
发明人： Richard C. Blish, II , Colin Hatchard , Ian Morgan
IPC分类号： H01L2144
CPC分类号： H01L23/3114 , H01L23/544 , H01L23/60 , H01L24/48 , H01L2223/54473 , H01L2224/05599 , H01L2224/48091 , H01L2224/4824 , H01L2224/85399 , H01L2924/00013 , H01L2924/00014 , H01L2924/01019 , H01L2924/01077 , H01L2924/10253 , H01L2924/12042 , H01L2224/29099 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： The present invention is a method for providing chip scale package. The method of the present invention includes providing a die with a first side, a second side, and a plurality of edges; applying a substance which protects against electrostatic discharge to the first side of the die and to the plurality of edges; and providing components on the second side of the die. The method of the present invention protects the chip scale package from electrostatic discharges. Markings may also be placed on the substance without damaging the chip in the package.
摘要翻译：本发明是提供芯片级封装的方法。本发明的方法包括提供具有第一侧，第二侧和多个边缘的管芯; 将防止静电放电的物质施加到模具的第一侧和多个边缘; 并且在模具的第二侧上提供部件。本发明的方法保护芯片级封装免受静电放电。标记也可以放在物质上，而不会损坏包装中的芯片。

3. 发明授权

US06181017B2 System for marking electrophoretic dies while reducing damage due to electrostatic discharge 有权
标题翻译：用于标记电泳模具的系统，同时减少由于静电放电造成的损坏
公开(公告)号：US06181017B2
公开(公告)日：2001-01-30
申请号：US09292769
申请日：1999-04-14
申请人： Colin Hatchard , Richard C. Blish, II , Daniel Yim
发明人： Colin Hatchard , Richard C. Blish, II , Daniel Yim
IPC分类号： H01L23544
CPC分类号： H01L23/544 , H01L2223/54406 , H01L2223/54473 , H01L2223/54486 , H01L2924/0002 , H01L2924/00
摘要： A system and method for marking a chip-scale package is disclosed. In one aspect, the chip-scale package includes a semiconductor die. The semiconductor die has an exposed portion substantially surrounded by the first coating. In this aspect, the method and system include applying a second coating to a first portion of the first coating and marking the second coating. The first coating is not completely penetrated by the marking. In a second aspect, the method and system include providing a chip-scale package. In this aspect, the method and system comprise providing a substrate, providing a semiconductor die coupled to a substrate, and providing a first coating. The semiconductor die has an exposed portion. The exposed portion is substantially surrounded by the first coating. In this aspect, the method and system further include providing a second coating substantially covering a first portion of the first coating. The second coating has a plurality of markings therein. The first coating is not completely penetrated by the plurality of markings.
摘要翻译：公开了一种用于标记芯片级封装的系统和方法。一方面，芯片级封装包括半导体管芯。半导体管芯具有基本被第一涂层包围的暴露部分。在这方面，该方法和系统包括将第二涂层施加到第一涂层的第一部分并标记第二涂层。第一层涂层未被标记完全渗透。在第二方面，该方法和系统包括提供芯片级封装。在这方面，该方法和系统包括提供衬底，提供耦合到衬底的半导体管芯，以及提供第一涂层。半导体管芯具有暴露部分。暴露部分基本上被第一涂层包围。在这方面，该方法和系统还包括提供基本上覆盖第一涂层的第一部分的第二涂层。第二涂层中有多个标记。第一涂层不被多个标记完全穿透。

4. 发明授权

US6049465A Signal carrying means including a carrier substrate and wire bonds for carrying signals between the cache and logic circuitry of a microprocessor 有权
标题翻译：信号承载装置包括载体基板和引线键合，用于在微处理器的高速缓存和逻辑电路之间传送信号
公开(公告)号：US6049465A
公开(公告)日：2000-04-11
申请号：US160830
申请日：1998-09-25
申请人： Richard C. Blish, II , Colin Hatchard , David Edward Lewis
发明人： Richard C. Blish, II , Colin Hatchard , David Edward Lewis
IPC分类号： G06F12/08 , H01L21/56 , H01L23/50 , H01L25/18 , H01L29/06 , H05K7/02
CPC分类号： H01L25/18 , G06F12/0893 , H01L21/563 , H01L23/50 , H01L24/73 , H01L2224/05599 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73257 , H01L2224/85399 , H01L24/48 , H01L29/0657 , H01L2924/00014 , H01L2924/01033 , H01L2924/10155 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15312 , H01L2924/15313 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107
摘要： The present invention provides a microprocessor, the microprocessor having a substrate with a first and a second side, the first and second sides being on opposite sides of the substrate. The microprocessor includes decoupling capacitors on the first side of the substrate; cache circuitry on the first side of the substrate; logic circuitry on the second side of the substrate; and a signal carrying means including a carrier substrate and wire bonds for carrying signals between the logic and cache circuitry.
摘要翻译：本发明提供一种微处理器，微处理器具有带有第一和第二侧面的基板，第一和第二侧面在基板的相对侧上。微处理器包括在衬底的第一侧上的去耦电容器; 在基板的第一面上的高速缓存电路; 衬底第二面上的逻辑电路; 以及包括载体衬底和引线键合的信号承载装置，用于在逻辑电路和高速缓存电路之间传送信号。

5. 发明授权

US6091157A Method to improve internal package delamination and wire bond reliability using non-homogeneous molding compound pellets 失效
标题翻译：使用非均匀成型复合粒料提高内包装分层和焊丝可靠性的方法
公开(公告)号：US6091157A
公开(公告)日：2000-07-18
申请号：US986085
申请日：1997-12-05
申请人： J. Courtney Black , Richard C. Blish, II , Colin D. Hatchard
发明人： J. Courtney Black , Richard C. Blish, II , Colin D. Hatchard
IPC分类号： H01L21/56 , H01L23/29 , H01L23/31
CPC分类号： H01L21/565 , H01L21/56 , H01L23/293 , H01L23/296 , H01L23/3135 , H01L23/3142 , H01L2224/05599 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/85399 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01012 , H01L2924/0102 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/10253 , H01L2924/14 , H01L2924/181
摘要： Method for implementing a multi-phase plastic package for electronic components, and packaged electronic components produced according to the method. The present invention contemplates the use of molding compounds having two or more discrete phases in a transfer molding process wherein a temperature differential is induced between the electronic component to be packaged and the mold of the molding apparatus prior to molding. Each of the molding compound phases, when used in a current transfer molding apparatus, generates a separate layer in the resultant package, and each of the resultant layers possesses certain unique properties. In its simplest implementation, the present invention provides a two-phase molding compound pellet which provides an outer layer containing mold release compounds to facilitate release of the completed packaged device from the mold, and an inner layer without mold release agents. Other implementations include multiple layers. One such implementation provides for an inner layer without flame retardants and a layer exterior to the inner layer containing flame retardants. In this manner, chemical interaction between the flame retardants and the encapsulated device is precluded. Other adjuncts may, with equal facility, be implemented in such additional layers as a given application may require.
摘要翻译：用于实现电子部件的多相塑料封装的方法，以及根据该方法制造的封装的电子部件。本发明考虑了在传递模塑过程中使用具有两个或更多个离散相的模制化合物，其中在待成型的电子部件与模制装置的模具之间引起温度差异。当在电流传递模塑装置中使用时，每个模塑料相在所得包装中产生单独的层，并且每个所得层具有一定的独特性质。在其最简单的实施方式中，本发明提供了一种两相模塑复合颗粒，其提供含有脱模化合物的外层，以便于将完成的包装装置从模具中释放，以及不具有脱模剂的内层。其他实现包括多个层。一种这样的实施方案提供了不含阻燃剂的内层和含有阻燃剂的内层外层。以这种方式，排除了阻燃剂和封装装置之间的化学相互作用。其他附件可以具有相同的设施，可以在给定应用可能需要的附加层中实现。

6. 发明授权

US5907561A Method to improve testing speed of memory 失效
标题翻译：提高内存测试速度的方法
公开(公告)号：US5907561A
公开(公告)日：1999-05-25
申请号：US992077
申请日：1997-12-17
申请人： Richard C. Blish, II , David E. Lewis
发明人： Richard C. Blish, II , David E. Lewis
IPC分类号： G11C29/10 , G06F11/00
CPC分类号： G11C29/10
摘要： A method of testing a semiconductor memory device using a parallel march pattern method of testing. All of the memory bits in a memory device are programmed to a first logic state. All of the memory bits in selected rows are programmed to a second logic state. All of the memory bits in rows adjacent to the rows programmed to the second logic state are read to determine if the memory bits programmed to the second logic state have caused the memory bits programmed to the first logic state in the adjacent rows to change logic state. The selected rows are determined by a periodicity value that can be values such as 4, 8, or 16. The periodicity determines the number of clock cycles needed to test the entire memory device. A periodicity of 8 requires only 8 clock cycles to test the entire memory device, regardless of the size of the memory device. The parallel march pattern method of testing can be by rows, by columns or by diagonals.
摘要翻译：使用并行行进模式测试方法测试半导体存储器件的方法。存储器件中的所有存储器位被编程为第一逻辑状态。所选行中的所有存储位都被编程为第二个逻辑状态。读取与被编程到第二逻辑状态的行相邻的行中的所有存储器位，以确定被编程到第二逻辑状态的存储器位是否已使得被编程到相邻行中的第一逻辑状态的存储器位改变逻辑状态。所选择的行由周期值确定，周期值可以是诸如4,8或16的值。周期性确定测试整个存储器件所需的时钟周期数。 8的周期性只需要8个时钟周期来测试整个存储器件，无论存储器件的大小如何。平行行进模式的测试方法可以是行，列或对角线。

7. 发明授权

US4870224A Integrated circuit package for surface mount technology 失效
标题翻译：用于表面贴装技术的集成电路封装
公开(公告)号：US4870224A
公开(公告)日：1989-09-26
申请号：US214219
申请日：1988-07-01
申请人： William D. Smith , Richard Dennis , Nicholas Brathwaite , Richard C. Blish, II
发明人： William D. Smith , Richard Dennis , Nicholas Brathwaite , Richard C. Blish, II
IPC分类号： H01L23/31 , H01L23/498 , H01L25/065 , H05K1/14 , H05K3/28 , H05K3/34
CPC分类号： H05K3/3405 , H01L23/315 , H01L23/49811 , H01L25/0655 , H01L2224/16225 , H01L2924/09701 , H01L2924/16251 , H05K1/141 , H05K2201/10386 , H05K3/284 , H05K3/3426 , Y10T29/49121
摘要： The present invention provides for an apparatus and a method for housing an integrated circuit device. The integrated circuit device is coupled to a ceramic substrate wherein contacts of the integrated circuit device mate with contacts on the substrate surface. Conductive lines then couple the contacts to the peripheral edges of the substrate where one set of ends of a lead frame assembly mates with the conductors. An encapsulation technique is used to encapsulate the device, such that only the other set of ends of the lead frame assembly extends from the package. In an alternative embodiment, the integrated circuit is hermetically sealed by having a hermetic cover disposed over the integrated circuit. In a second alternative embodiment, the substrate is capable of having disposed upon it multiple integrated circuits. The present invention provides for a significant increase of lead count to die size ratio.
摘要翻译：本发明提供一种用于容纳集成电路装置的装置和方法。集成电路器件耦合到陶瓷衬底，其中集成电路器件的触点与衬底表面上的触点配合。导线然后将触点耦合到衬底的周边边缘，其中引线框架组件的一组端部与导体配合。使用封装技术来封装器件，使得仅引线框架组件的另一组端部从封装延伸。在替代实施例中，集成电路通过设置在集成电路上方的密封盖来密封。在第二替代实施例中，基板能够在其上放置多个集成电路。本发明提供了引线数对芯片尺寸比的显着增加。

8. 发明授权

US08384210B1 Thermal interface material and semiconductor component including the thermal interface material 有权
标题翻译：热界面材料和包括热界面材料的半导体组件
公开(公告)号：US08384210B1
公开(公告)日：2013-02-26
申请号：US11147598
申请日：2005-06-07
申请人： Richard C. Blish, II , James L. Hayward
发明人： Richard C. Blish, II , James L. Hayward
IPC分类号： H01L23/34
CPC分类号： H01L23/42 , H01L23/10 , H01L23/3736 , H01L23/49816 , H01L2224/16225 , H01L2224/73253 , H01L2924/15311
摘要： A thermal interface material for use in manufacturing a semiconductor component and a method for manufacturing the semiconductor component. The thermal interface material includes a metallic element in combination with either antimony or tin. Suitable metallic elements include gallium or indium. The concentration of antimony or tin is about 2 percent or less by weight of the thermal interface material. A semiconductor chip is mounted to a support substrate and the thermal interface material is disposed on the semiconductor chip. A lid or a heatsink is coupled to the semiconductor chip via the thermal interface material.
摘要翻译：一种用于制造半导体部件的热界面材料及其制造方法。热界面材料包括与锑或锡组合的金属元素。合适的金属元素包括镓或铟。锑或锡的浓度约为热界面材料重量的2％或更少。半导体芯片安装在支撑基板上，热界面材料设置在半导体芯片上。盖子或散热器经由热界面材料耦合到半导体芯片。

9. 发明授权

US06803653B1 Apparatus for suppressing packaged semiconductor chip curvature while minimizing thermal impedance and maximizing speed/reliability 有权
标题翻译：用于抑制封装的半导体芯片曲率同时最小化热阻抗并使速度/可靠性最大化的装置
公开(公告)号：US06803653B1
公开(公告)日：2004-10-12
申请号：US10010392
申请日：2001-12-07
申请人： Robert E. Likins , Richard C. Blish, II , Sharad M. Shah , Sidharth Sidharth , Devendra Natekar
发明人： Robert E. Likins , Richard C. Blish, II , Sharad M. Shah , Sidharth Sidharth , Devendra Natekar
IPC分类号： H01L2334
CPC分类号： H01L23/36 , H01L23/42 , H01L2224/16 , H01L2224/73253 , H01L2924/00014 , H01L2924/01322 , H01L2924/10253 , H01L2924/12044 , H01L2924/3011 , H01L2924/3511 , H01L2924/00 , H01L2224/0401
摘要： A semiconductor structure includes a substrate and a semiconductor devices secured to the substrate. A stabilizing member is secured to the semiconductor device, and has a coefficient of thermal expansion which is substantially the same as the coefficient of thermal expansion of the substrate. The bending stiffness of the substrate is substantially the same as the bending stiffness of the stabilizing member, wherein: bending stiffness=Et3, with E=Young's modulus, and t=thickness. In another embodiment, a stabilizing member is secured to the substrate, and has a coefficient of thermal expansion which is substantially the same as the coefficient of thermal expansion of the die. The bending stiffness of the die is substantially the same as the bending stiffness of the stabilizing member, with bending stiffness defined as above.
摘要翻译：半导体结构包括衬底和固定到衬底的半导体器件。稳定构件被固定到半导体器件，并且具有基本上与衬底的热膨胀系数相同的热膨胀系数。基板的弯曲刚度基本上与稳定构件的弯曲刚度相同，其中：在另一个实施例中，稳定构件固定到基板上，并且具有与系数相同的热膨胀系数模具的热膨胀。模具的弯曲刚度基本上与稳定构件的弯曲刚度相同，具有如上所述的弯曲刚度。

10. 发明授权

US06429657B1 Apparatus for improving image depth resolution in a magnetic field imaging apparatus 失效
标题翻译：用于改善磁场成像装置中的图像深度分辨率的装置
公开(公告)号：US06429657B1
公开(公告)日：2002-08-06
申请号：US09757116
申请日：2001-01-09
申请人： Richard C. Blish, II
发明人： Richard C. Blish, II
IPC分类号： G01V300
CPC分类号： G01V3/081
摘要： A magnetic field imaging apparatus for sensing a magnetic field generated by current flowing in the semiconductor device includes a pair of sensing devices which may be focused at a chosen depth in a semiconductor device. The sensing devices may be movable so that they may be focused at different focal points. The apparatus may also include three or more sensing devices, which can be chosen to operate in tears to define a variety of focus depths in a semiconductor device.
摘要翻译：用于感测由在半导体器件中流动的电流产生的磁场的磁场成像装置包括可以在半导体器件中以选定深度聚焦的一对感测装置。感测装置可以是可移动的，使得它们可以在不同的焦点处聚焦。该装置还可以包括三个或更多个感测装置，其可被选择为在半导体装置中限定多种聚焦深度的撕裂。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式