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1. 发明授权

US06181017B2 System for marking electrophoretic dies while reducing damage due to electrostatic discharge 有权
标题翻译：用于标记电泳模具的系统，同时减少由于静电放电造成的损坏
公开(公告)号：US06181017B2
公开(公告)日：2001-01-30
申请号：US09292769
申请日：1999-04-14
申请人： Colin Hatchard , Richard C. Blish, II , Daniel Yim
发明人： Colin Hatchard , Richard C. Blish, II , Daniel Yim
IPC分类号： H01L23544
CPC分类号： H01L23/544 , H01L2223/54406 , H01L2223/54473 , H01L2223/54486 , H01L2924/0002 , H01L2924/00
摘要： A system and method for marking a chip-scale package is disclosed. In one aspect, the chip-scale package includes a semiconductor die. The semiconductor die has an exposed portion substantially surrounded by the first coating. In this aspect, the method and system include applying a second coating to a first portion of the first coating and marking the second coating. The first coating is not completely penetrated by the marking. In a second aspect, the method and system include providing a chip-scale package. In this aspect, the method and system comprise providing a substrate, providing a semiconductor die coupled to a substrate, and providing a first coating. The semiconductor die has an exposed portion. The exposed portion is substantially surrounded by the first coating. In this aspect, the method and system further include providing a second coating substantially covering a first portion of the first coating. The second coating has a plurality of markings therein. The first coating is not completely penetrated by the plurality of markings.
摘要翻译：公开了一种用于标记芯片级封装的系统和方法。一方面，芯片级封装包括半导体管芯。半导体管芯具有基本被第一涂层包围的暴露部分。在这方面，该方法和系统包括将第二涂层施加到第一涂层的第一部分并标记第二涂层。第一层涂层未被标记完全渗透。在第二方面，该方法和系统包括提供芯片级封装。在这方面，该方法和系统包括提供衬底，提供耦合到衬底的半导体管芯，以及提供第一涂层。半导体管芯具有暴露部分。暴露部分基本上被第一涂层包围。在这方面，该方法和系统还包括提供基本上覆盖第一涂层的第一部分的第二涂层。第二涂层中有多个标记。第一涂层不被多个标记完全穿透。

2. 发明授权

US06331735B1 Method to improve chip scale package electrostatic discharge performance and suppress marking artifacts 有权
公开(公告)号：US06331735B1
公开(公告)日：2001-12-18
申请号：US09161062
申请日：1998-09-25
申请人： Richard C. Blish, II , Colin Hatchard , Ian Morgan
发明人： Richard C. Blish, II , Colin Hatchard , Ian Morgan
IPC分类号： H01L2348
CPC分类号： H01L23/3114 , H01L23/544 , H01L23/60 , H01L24/48 , H01L2223/54473 , H01L2224/05599 , H01L2224/48091 , H01L2224/4824 , H01L2224/85399 , H01L2924/00013 , H01L2924/00014 , H01L2924/01019 , H01L2924/01077 , H01L2924/10253 , H01L2924/12042 , H01L2224/29099 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： The present invention is a method for providing chip scale package. The method of the present invention includes providing a die with a first side, a second side, and a plurality of edges; applying a substance which protects against electrostatic discharge to the first side of the die and to the plurality of edges; and providing components on the second side of the die. The method of the present invention protects the chip scale package from electrostatic discharges. Markings may also be placed on the substance without damaging the chip in the package.

3. 发明授权

US06495393B2 Method to improve chip scale package electrostatic discharge performance and suppress marking artifacts 失效
标题翻译：提高芯片级封装静电放电性能并抑制标记伪影的方法
公开(公告)号：US06495393B2
公开(公告)日：2002-12-17
申请号：US09836747
申请日：2001-04-17
申请人： Richard C. Blish, II , Colin Hatchard , Ian Morgan
发明人： Richard C. Blish, II , Colin Hatchard , Ian Morgan
IPC分类号： H01L2144
CPC分类号： H01L23/3114 , H01L23/544 , H01L23/60 , H01L24/48 , H01L2223/54473 , H01L2224/05599 , H01L2224/48091 , H01L2224/4824 , H01L2224/85399 , H01L2924/00013 , H01L2924/00014 , H01L2924/01019 , H01L2924/01077 , H01L2924/10253 , H01L2924/12042 , H01L2224/29099 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： The present invention is a method for providing chip scale package. The method of the present invention includes providing a die with a first side, a second side, and a plurality of edges; applying a substance which protects against electrostatic discharge to the first side of the die and to the plurality of edges; and providing components on the second side of the die. The method of the present invention protects the chip scale package from electrostatic discharges. Markings may also be placed on the substance without damaging the chip in the package.
摘要翻译：本发明是提供芯片级封装的方法。本发明的方法包括提供具有第一侧，第二侧和多个边缘的管芯; 将防止静电放电的物质施加到模具的第一侧和多个边缘; 并且在模具的第二侧上提供部件。本发明的方法保护芯片级封装免受静电放电。标记也可以放在物质上，而不会损坏包装中的芯片。

4. 发明授权

US06320266B1 Technique for reducing breakage of thinned flip-chip multi-layer integrated circuit devices 失效
标题翻译：减薄倒装芯片多层集成电路器件破损的技术
公开(公告)号：US06320266B1
公开(公告)日：2001-11-20
申请号：US09273227
申请日：1999-03-18
申请人： Colin Hatchard
发明人： Colin Hatchard
IPC分类号： H01L2348
CPC分类号： H01L21/6836 , B24B37/30 , H01L2221/68327 , H01L2224/02381 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/16 , H01L2924/01077
摘要： Aspects for supporting thinning of a flip-chip device with reduced risk of breakage are described. An exemplary apparatus aspect includes a multi-layer integrated circuit device oriented in a flip-chip orientation, and a support substrate transparent to a light source of a predetermined wavelength. The apparatus further includes an adhesive, the adhesive affixing the multi-layer integrated circuit device to the support structure during thinning of the multi-layer integrated circuit device from a backside and sufficiently releasing the multi-layer integrated circuit device when exposed to the light source of the predetermined wavelength through the support substrate after thinning is completed to reduce breakage risk for the thinned multi-layer integrated circuit device.
摘要翻译：描述了减少破损风险的倒装芯片装置的薄化的方面。示例性装置方面包括以倒装芯片取向定向的多层集成电路装置和对预定波长的光源透明的支撑基板。该设备还包括粘合剂，粘合剂将多层集成电路器件固定在支撑结构上，在多层集成电路器件从背面减薄时，当暴露于光源时充分释放多层集成电路器件在减薄之后通过支撑基板的预定波长的预定波长，以减少薄型多层集成电路器件的断裂风险。

5. 发明授权

US6049465A Signal carrying means including a carrier substrate and wire bonds for carrying signals between the cache and logic circuitry of a microprocessor 有权
标题翻译：信号承载装置包括载体基板和引线键合，用于在微处理器的高速缓存和逻辑电路之间传送信号
公开(公告)号：US6049465A
公开(公告)日：2000-04-11
申请号：US160830
申请日：1998-09-25
申请人： Richard C. Blish, II , Colin Hatchard , David Edward Lewis
发明人： Richard C. Blish, II , Colin Hatchard , David Edward Lewis
IPC分类号： G06F12/08 , H01L21/56 , H01L23/50 , H01L25/18 , H01L29/06 , H05K7/02
CPC分类号： H01L25/18 , G06F12/0893 , H01L21/563 , H01L23/50 , H01L24/73 , H01L2224/05599 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73257 , H01L2224/85399 , H01L24/48 , H01L29/0657 , H01L2924/00014 , H01L2924/01033 , H01L2924/10155 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15312 , H01L2924/15313 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107
摘要： The present invention provides a microprocessor, the microprocessor having a substrate with a first and a second side, the first and second sides being on opposite sides of the substrate. The microprocessor includes decoupling capacitors on the first side of the substrate; cache circuitry on the first side of the substrate; logic circuitry on the second side of the substrate; and a signal carrying means including a carrier substrate and wire bonds for carrying signals between the logic and cache circuitry.
摘要翻译：本发明提供一种微处理器，微处理器具有带有第一和第二侧面的基板，第一和第二侧面在基板的相对侧上。微处理器包括在衬底的第一侧上的去耦电容器; 在基板的第一面上的高速缓存电路; 衬底第二面上的逻辑电路; 以及包括载体衬底和引线键合的信号承载装置，用于在逻辑电路和高速缓存电路之间传送信号。

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