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1. 发明授权

US07179760B2 Bilayer cap structure including HDP/bHDP films for conductive metallization and method of making same 失效
标题翻译：双层盖结构，包括用于导电金属化的HDP / bHDP膜及其制造方法
公开(公告)号：US07179760B2
公开(公告)日：2007-02-20
申请号：US10908833
申请日：2005-05-27
申请人： Richard A. Conti , Thomas F. Houghton , Michael F. Lofaro , Jeffery B. Maxson , Ann H. McDonald , Yun-Yu Wang , Keith Kwong Hon Wong , Daewon Yang
发明人： Richard A. Conti , Thomas F. Houghton , Michael F. Lofaro , Jeffery B. Maxson , Ann H. McDonald , Yun-Yu Wang , Keith Kwong Hon Wong , Daewon Yang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L23/53238 , H01L21/28556 , H01L21/76849 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a bilayer cap structure for interconnect structures that comprise copper metallization or other conductive metallization. Such bilayer cap structure includes a first cap layer formed by an unbiased high density plasma (HDP) chemical vapor deposition process, and a second cap layer over the first cap layer, where the second cap layer is formed by a biased high density plasma (bHDP) chemical vapor deposition process. During the bHDP chemical vapor deposition process, a low AC bias power is applied to the substrate to increase the ion bombardment on the substrate surface and to induce resputtering of the capping material, thereby forming a seamless second cap layer with excellent reactive ion etching (RIE) selectivity.
摘要翻译：本发明涉及一种用于互连结构的双层盖结构，其包括铜金属化或其它导电金属化。这种双层盖结构包括通过无偏高密度等离子体（HDP）化学气相沉积工艺形成的第一盖层和在第一盖层上的第二盖层，其中第二盖层由偏置的高密度等离子体（bHDP ）化学气相沉积工艺。在bHDP化学气相沉积工艺期间，将低AC偏置功率施加到衬底上以增加衬底表面上的离子轰击并引起封盖材料的再溅射，从而形成具有优异的反应离子蚀刻（RIE）的无缝第二帽层）选择性。

2. 发明申请

US20080146039A1 METHOD TO REDUCE PLASMA CHARGE DAMAGE FROM HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION (HDP-CVD) PROCESS 审中-公开
标题翻译：降低高密度等离子体化学气相沉积（HDP-CVD）工艺的等离子体电荷损失的方法
公开(公告)号：US20080146039A1
公开(公告)日：2008-06-19
申请号：US11611212
申请日：2006-12-15
申请人： Daewon Yang , Jeffery B. Maxson , Ann N. McDonald
发明人： Daewon Yang , Jeffery B. Maxson , Ann N. McDonald
IPC分类号： H01L21/283
CPC分类号： C23C16/50
摘要： A method of processing wafers within a high density plasma chemical vapor deposition chamber comprises setting a plasma charge level within the chamber at a zero power level and, while the plasma charge level within the chamber is at the zero power level, moving a wafer into the chamber. Then, the method sets the plasma charge level to a second power level higher than zero after the wafer is moved into the chamber and performs a chemical vapor deposition process on the wafer within the chamber. After performing the chemical vapor deposition process, the method moves the wafer to a non-plasma region within the chamber. Then, after moving the wafer to the non-plasma region within the chamber, the method again sets the plasma charge level within the chamber at the zero power level. Next, after setting the plasma charge level within the chamber at the zero power level, the method opens the door of the chamber and, while the plasma charge level within the chamber is at the zero power level, the method removes the wafer from the chamber through the door of the chamber.
摘要翻译：在高密度等离子体化学气相沉积室内处理晶片的方法包括在零功率水平下设置室内的等离子体电荷水平，并且在室内的等离子体电荷水平处于零功率水平的同时，将晶片移动到房间。然后，该方法将晶片移入腔室之后，将等离子体电荷电平设置为高于零的第二功率电平，并在腔室内的晶片上执行化学气相沉积工艺。在执行化学气相沉积工艺之后，该方法将晶片移动到室内的非等离子体区域。然后，在将晶片移动到室内的非等离子体区域之后，该方法再次将室内的等离子体电荷水平设置在零功率水平。接下来，在将腔室内的等离子体充电水平设置在零功率水平之后，该方法打开腔室的门，并且在室内的等离子体充电水平处于零功率水平的同时，该方法将晶片从腔室通过房间的门。

3. 发明申请

US20110237067A1 STRUCTURE AND METHOD OF CREATING ENTIRELY SELF-ALIGNED METALLIC CONTACTS 有权
标题翻译：创建完全自对准金属接触的结构和方法
公开(公告)号：US20110237067A1
公开(公告)日：2011-09-29
申请号：US13155056
申请日：2011-06-07
申请人： Jeffery B. Maxson , Cung Do Tran , Huilong Zhu
发明人： Jeffery B. Maxson , Cung Do Tran , Huilong Zhu
IPC分类号： H01L21/768
CPC分类号： H01L29/7833 , H01L21/28052 , H01L21/288 , H01L21/76879 , H01L21/76885 , H01L21/76897 , H01L29/41783 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer. The structure also includes a first metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the first metal semiconductor alloy layer and a second metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the second metal semiconductor alloy layer.
摘要翻译：提供具有完全自对准金属接触的半导体结构。半导体结构包括位于半导体衬底的表面上的至少一个场效应晶体管。所述至少一个场效应晶体管包括包括多晶硅的下层和第一金属半导体合金的上层的栅极导体堆叠，所述栅极导体堆叠具有包括至少一个间隔物的侧壁。该结构还包括位于半导体衬底内的第二金属半导体合金层，该第二金属半导体合金层位于该至少一个间隔物的覆盖区。该结构还包括第一金属接触，其包含元素周期表第VIII族或第IB族的金属，以及位于第一金属半导体合金层上并自对准的W，B，P，Mo和Re中的至少一种以及包含元素周期表第VIII族或第IB族的金属和第二金属半导体合金层自对准的W，B，P，Mo和Re中的至少一种的第二金属接触体。

4. 发明授权

US07964923B2 Structure and method of creating entirely self-aligned metallic contacts 有权
标题翻译：创建完全自对准的金属触点的结构和方法
公开(公告)号：US07964923B2
公开(公告)日：2011-06-21
申请号：US11970165
申请日：2008-01-07
申请人： Jeffery B. Maxson , Cung Do Tran , Huilong Zhu
发明人： Jeffery B. Maxson , Cung Do Tran , Huilong Zhu
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L21/28052 , H01L21/288 , H01L21/76879 , H01L21/76885 , H01L21/76897 , H01L29/41783 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer. The structure also includes a first metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the first metal semiconductor alloy layer and a second metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the second metal semiconductor alloy layer.
摘要翻译：提供具有完全自对准金属接触的半导体结构。半导体结构包括位于半导体衬底的表面上的至少一个场效应晶体管。所述至少一个场效应晶体管包括包括多晶硅的下层和第一金属半导体合金的上层的栅极导体堆叠，所述栅极导体堆叠具有包括至少一个间隔物的侧壁。该结构还包括位于半导体衬底内的第二金属半导体合金层，该第二金属半导体合金层位于该至少一个间隔物的覆盖区。该结构还包括第一金属接触，其包含元素周期表第VIII族或第IB族的金属，以及位于第一金属半导体合金层上并自对准的W，B，P，Mo和Re中的至少一种以及包含元素周期表第VIII族或第IB族的金属和第二金属半导体合金层自对准的W，B，P，Mo和Re中的至少一种的第二金属接触体。

5. 发明授权

US08298934B2 Structure and method of creating entirely self-aligned metallic contacts 有权
标题翻译：创建完全自对准的金属触点的结构和方法
公开(公告)号：US08298934B2
公开(公告)日：2012-10-30
申请号：US13155056
申请日：2011-06-07
申请人： Jeffery B. Maxson , Cung Do Tran , Huilong Zhu
发明人： Jeffery B. Maxson , Cung Do Tran , Huilong Zhu
IPC分类号： H01L21/4763
CPC分类号： H01L29/7833 , H01L21/28052 , H01L21/288 , H01L21/76879 , H01L21/76885 , H01L21/76897 , H01L29/41783 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer. The structure also includes a first metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the first metal semiconductor alloy layer and a second metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the second metal semiconductor alloy layer.
摘要翻译：提供具有完全自对准金属接触的半导体结构。半导体结构包括位于半导体衬底的表面上的至少一个场效应晶体管。所述至少一个场效应晶体管包括包括多晶硅的下层和第一金属半导体合金的上层的栅极导体堆叠，所述栅极导体堆叠具有包括至少一个间隔物的侧壁。该结构还包括位于半导体衬底内的第二金属半导体合金层，该第二金属半导体合金层位于该至少一个间隔物的覆盖区。该结构还包括第一金属接触，其包含元素周期表第VIII族或第IB族的金属，以及位于第一金属半导体合金层上并自对准的W，B，P，Mo和Re中的至少一种以及包含元素周期表第VIII族或第IB族的金属和第二金属半导体合金层自对准的W，B，P，Mo和Re中的至少一种的第二金属接触体。

6. 发明授权

US08106515B2 Local metallization and use thereof in semiconductor devices 有权
标题翻译：局部金属化及其在半导体器件中的应用
公开(公告)号：US08106515B2
公开(公告)日：2012-01-31
申请号：US12795681
申请日：2010-06-08
申请人： Jeffery B. Maxson , Aurelia A. Suwarno-Handayana , Shamas M. Ummer , Kenneth J. Giewont , Scott Richard Stiffler
发明人： Jeffery B. Maxson , Aurelia A. Suwarno-Handayana , Shamas M. Ummer , Kenneth J. Giewont , Scott Richard Stiffler
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76825 , H01L21/7682 , H01L21/76838 , H01L21/76895 , H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention provides a method of creating local metallization in a semiconductor structure, and the use of local metallization so created in semiconductor structures. In one respect, the method includes forming an insulating layer on top of a semiconductor substrate; creating a plurality of voids inside the insulating layer, with the plurality of voids spanning across a predefined area and being substantially confined within a range of depth below a top surface of the insulating layer; creating at least one via hole in the insulating layer, with the via hole passing through the predefined area; and filling the via hole, and the plurality of voids inside the insulating layer through at least the via hole, with a conductive material to form a local metallization. A semiconductor structure having the local metallization is also provided.
摘要翻译：本发明的实施例提供了一种在半导体结构中产生局部金属化的方法，以及如此在半导体结构中产生的局部金属化的使用。在一个方面，该方法包括在半导体衬底的顶部上形成绝缘层; 在所述绝缘层内形成多个空隙，所述多个空隙横跨预定区域并且基本上限制在所述绝缘层的顶表面下方的深度范围内; 在所述绝缘层中形成至少一个通孔，所述通孔穿过所述预定区域; 以及通过至少通孔将绝缘层内的通孔和绝缘层中的多个空隙用导电材料填充以形成局部金属化。还提供了具有局部金属化的半导体结构。

7. 发明申请

US20090174006A1 STRUCTURE AND METHOD OF CREATING ENTIRELY SELF-ALIGNED METALLIC CONTACTS 有权
标题翻译：创建完全自对准金属接触的结构和方法
公开(公告)号：US20090174006A1
公开(公告)日：2009-07-09
申请号：US11970165
申请日：2008-01-07
申请人： Jeffery B. Maxson , Cung Do Tran , Huilong Zhu
发明人： Jeffery B. Maxson , Cung Do Tran , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/4763
CPC分类号： H01L29/7833 , H01L21/28052 , H01L21/288 , H01L21/76879 , H01L21/76885 , H01L21/76897 , H01L29/41783 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer. The structure also includes a first metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the first metal semiconductor alloy layer and a second metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the second metal semiconductor alloy layer.
摘要翻译：提供具有完全自对准金属接触的半导体结构。半导体结构包括位于半导体衬底的表面上的至少一个场效应晶体管。所述至少一个场效应晶体管包括包括多晶硅的下层和第一金属半导体合金的上层的栅极导体堆叠，所述栅极导体堆叠具有包括至少一个间隔物的侧壁。该结构还包括位于半导体衬底内的第二金属半导体合金层，该第二金属半导体合金层位于该至少一个间隔物的覆盖区。该结构还包括第一金属接触，其包含元素周期表第VIII族或第IB族的金属，以及位于第一金属半导体合金层上并自对准的W，B，P，Mo和Re中的至少一种以及包含元素周期表第VIII族或第IB族的金属和第二金属半导体合金层自对准的W，B，P，Mo和Re中的至少一种的第二金属接触体。

8. 发明授权

US07807570B1 Local metallization and use thereof in semiconductor devices 失效
标题翻译：局部金属化及其在半导体器件中的应用
公开(公告)号：US07807570B1
公开(公告)日：2010-10-05
申请号：US12482763
申请日：2009-06-11
申请人： Jeffery B. Maxson , Aurelia A. Suwarno-Handayana , Shamas M. Ummer , Kenneth J. Giewont , Scott Richard Stiffler
发明人： Jeffery B. Maxson , Aurelia A. Suwarno-Handayana , Shamas M. Ummer , Kenneth J. Giewont , Scott Richard Stiffler
IPC分类号： H01L21/44
CPC分类号： H01L21/76825 , H01L21/7682 , H01L21/76838 , H01L21/76895 , H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention provides a method of creating local metallization in a semiconductor structure, and the use of local metallization so created in semiconductor structures. In one respect, the method includes forming an insulating layer on top of a semiconductor substrate; creating a plurality of voids inside the insulating layer, with the plurality of voids spanning across a predefined area and being substantially confined within a range of depth below a top surface of the insulating layer; creating at least one via hole in the insulating layer, with the via hole passing through the predefined area; and filling the via hole, and the plurality of voids inside the insulating layer through at least the via hole, with a conductive material to form a local metallization. A semiconductor structure having the local metallization is also provided.
摘要翻译：本发明的实施例提供了一种在半导体结构中产生局部金属化的方法，以及如此在半导体结构中产生的局部金属化的使用。在一个方面，该方法包括在半导体衬底的顶部上形成绝缘层; 在所述绝缘层内形成多个空隙，所述多个空隙横跨预定区域并且基本上限制在所述绝缘层的顶表面下方的深度范围内; 在所述绝缘层中形成至少一个通孔，所述通孔穿过所述预定区域; 以及通过至少通孔将绝缘层内的通孔和绝缘层中的多个空隙用导电材料填充以形成局部金属化。还提供了具有局部金属化的半导体结构。

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