专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07807570B1 Local metallization and use thereof in semiconductor devices 失效
标题翻译：局部金属化及其在半导体器件中的应用
公开(公告)号：US07807570B1
公开(公告)日：2010-10-05
申请号：US12482763
申请日：2009-06-11
申请人： Jeffery B. Maxson , Aurelia A. Suwarno-Handayana , Shamas M. Ummer , Kenneth J. Giewont , Scott Richard Stiffler
发明人： Jeffery B. Maxson , Aurelia A. Suwarno-Handayana , Shamas M. Ummer , Kenneth J. Giewont , Scott Richard Stiffler
IPC分类号： H01L21/44
CPC分类号： H01L21/76825 , H01L21/7682 , H01L21/76838 , H01L21/76895 , H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention provides a method of creating local metallization in a semiconductor structure, and the use of local metallization so created in semiconductor structures. In one respect, the method includes forming an insulating layer on top of a semiconductor substrate; creating a plurality of voids inside the insulating layer, with the plurality of voids spanning across a predefined area and being substantially confined within a range of depth below a top surface of the insulating layer; creating at least one via hole in the insulating layer, with the via hole passing through the predefined area; and filling the via hole, and the plurality of voids inside the insulating layer through at least the via hole, with a conductive material to form a local metallization. A semiconductor structure having the local metallization is also provided.
摘要翻译：本发明的实施例提供了一种在半导体结构中产生局部金属化的方法，以及如此在半导体结构中产生的局部金属化的使用。在一个方面，该方法包括在半导体衬底的顶部上形成绝缘层; 在所述绝缘层内形成多个空隙，所述多个空隙横跨预定区域并且基本上限制在所述绝缘层的顶表面下方的深度范围内; 在所述绝缘层中形成至少一个通孔，所述通孔穿过所述预定区域; 以及通过至少通孔将绝缘层内的通孔和绝缘层中的多个空隙用导电材料填充以形成局部金属化。还提供了具有局部金属化的半导体结构。

2. 发明授权

US08106515B2 Local metallization and use thereof in semiconductor devices 有权
标题翻译：局部金属化及其在半导体器件中的应用
公开(公告)号：US08106515B2
公开(公告)日：2012-01-31
申请号：US12795681
申请日：2010-06-08
申请人： Jeffery B. Maxson , Aurelia A. Suwarno-Handayana , Shamas M. Ummer , Kenneth J. Giewont , Scott Richard Stiffler
发明人： Jeffery B. Maxson , Aurelia A. Suwarno-Handayana , Shamas M. Ummer , Kenneth J. Giewont , Scott Richard Stiffler
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76825 , H01L21/7682 , H01L21/76838 , H01L21/76895 , H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention provides a method of creating local metallization in a semiconductor structure, and the use of local metallization so created in semiconductor structures. In one respect, the method includes forming an insulating layer on top of a semiconductor substrate; creating a plurality of voids inside the insulating layer, with the plurality of voids spanning across a predefined area and being substantially confined within a range of depth below a top surface of the insulating layer; creating at least one via hole in the insulating layer, with the via hole passing through the predefined area; and filling the via hole, and the plurality of voids inside the insulating layer through at least the via hole, with a conductive material to form a local metallization. A semiconductor structure having the local metallization is also provided.
摘要翻译：本发明的实施例提供了一种在半导体结构中产生局部金属化的方法，以及如此在半导体结构中产生的局部金属化的使用。在一个方面，该方法包括在半导体衬底的顶部上形成绝缘层; 在所述绝缘层内形成多个空隙，所述多个空隙横跨预定区域并且基本上限制在所述绝缘层的顶表面下方的深度范围内; 在所述绝缘层中形成至少一个通孔，所述通孔穿过所述预定区域; 以及通过至少通孔将绝缘层内的通孔和绝缘层中的多个空隙用导电材料填充以形成局部金属化。还提供了具有局部金属化的半导体结构。

3. 发明授权

US06531375B1 Method of forming a body contact using BOX modification 失效
标题翻译：使用BOX修饰形成身体接触的方法
公开(公告)号：US06531375B1
公开(公告)日：2003-03-11
申请号：US09955375
申请日：2001-09-18
申请人： Kenneth J. Giewont , Eric Adler , Neena Garg , Michael J. Hargrove , Charles W. Koburger, III , Junedong Lee , Dominic J. Schepis , Isabel Ying Yang
发明人： Kenneth J. Giewont , Eric Adler , Neena Garg , Michael J. Hargrove , Charles W. Koburger, III , Junedong Lee , Dominic J. Schepis , Isabel Ying Yang
IPC分类号： H01L2176
CPC分类号： H01L21/76264 , H01L21/76267
摘要： A novel method for forming substrate contact regions on a SOI substrate without requiring additional space, and in order to provide lower diffusion capacitance. The method utilizes known semiconductor processing techniques. This method for selectively modifying the BOX region of a SOI substrate involves first providing a silicon substrate. Then, ion implanting the base using SIMOX techniques (e.g. O2 implant) is accomplished. Next, the substrate is photopatterned to protect the modified BOX region. Then, further ion implanting using a “touch-up” O2 implant is accomplished, thereby resulting in a good quality BOX as typically practiced. The final step is annealing the substrate. The area of the substrate, which had a mask present, would not receive the “touch-up” O2 implant (second ion implant), which in turn would result in a leaky BOX.
摘要翻译：一种用于在SOI衬底上形成衬底接触区而不需要额外空间的新方法，并且为了提供较低的扩散电容。该方法利用已知的半导体处理技术。这种用于选择性地修改SOI衬底的BOX区域的方法包括首先提供硅衬底。然后，使用SIMOX技术（例如，O 2注入）离子注入基底。接下来，对基板进行光图案化以保护修改的BOX区域。然后，使用“接触式”O2注入进一步进行离子注入，从而得到通常实施的良好质量BOX。最后一步是退火基板。存在掩模的衬底的区域将不会接收“接触”O 2注入（第二离子注入），这反过来将导致泄漏BOX。

4. 发明授权

US06531411B1 Surface roughness improvement of SIMOX substrates by controlling orientation of angle of starting material 失效
标题翻译：通过控制起始材料的角度取向，SIMOX基板的表面粗糙度提高
公开(公告)号：US06531411B1
公开(公告)日：2003-03-11
申请号：US10007845
申请日：2001-11-05
申请人： Anthony G. Domenicucci , Neena Garg , Kenneth J. Giewont , Richard J. Murphy , Gerd Pfeiffer , Gregory D. Pomarico , Frank J. Schmidt, Jr. , Terrance M. Tornatore
发明人： Anthony G. Domenicucci , Neena Garg , Kenneth J. Giewont , Richard J. Murphy , Gerd Pfeiffer , Gregory D. Pomarico , Frank J. Schmidt, Jr. , Terrance M. Tornatore
IPC分类号： H01L21461
CPC分类号： H01L21/76243 , Y10S977/721 , Y10S977/779 , Y10S977/856 , Y10S977/863 , Y10S977/881 , Y10S977/888 , Y10S977/90
摘要： A method of improving surface morphology of a semiconductor substrate when using an SOI technique comprises providing a silicon ingot positioned on a support member, orientating the silicon ingot in relation to the support member, and a cutting device, and cutting the silicon ingot along about a (100) crystal plane of the silicon ingot, preferably using a wire saw. This then provides a silicon substrate having an initial surface defining a miscut angle which is less than about 0.15 degrees from the (100) crystal plane. The method then comprises processing the silicon substrate using SIMOX processing, which includes implanting oxygen atoms in the silicon substrate to form a buried oxide layer and annealing the silicon substrate to provide a final substrate surface. Finally, the method includes accepting the final substrate surface for further processing when the final substrate surface measures between 2-20 Å RMS using an atomic force microscopy technique.
摘要翻译：当使用SOI技术时，改进半导体衬底的表面形态的方法包括提供位于支撑构件上的硅锭，使硅锭相对于支撑构件定向，以及切割装置，并且沿着约（100）晶锭的晶面，优选使用线锯。这样就提供了具有限定与（100）晶面小于约0.15度的误差角的初始表面的硅衬底。该方法然后包括使用SIMOX处理来处理硅衬底，其包括在硅衬底中注入氧原子以形成掩埋氧化物层并退火硅衬底以提供最终衬底表面。最后，该方法包括当最终的基底表面使用原子力显微镜技术测量2-20ÅRMS时，接受最终的基底表面进行进一步的处理。

5. 发明授权

US06495429B1 Controlling internal thermal oxidation and eliminating deep divots in SIMOX by chlorine-based annealing 有权
标题翻译：通过氯基退火控制内部热氧化和消除SIMOX中的深刻
公开(公告)号：US06495429B1
公开(公告)日：2002-12-17
申请号：US10055139
申请日：2002-01-23
申请人： Michael E. Adamcek , Anthony G. Domenicucci , Stephen R. Fox , Neena Garg , Kenneth J. Giewont , Thomas R. Kupiec , Junedong Lee , Devendra K. Sadana
发明人： Michael E. Adamcek , Anthony G. Domenicucci , Stephen R. Fox , Neena Garg , Kenneth J. Giewont , Thomas R. Kupiec , Junedong Lee , Devendra K. Sadana
IPC分类号： H01L2176
CPC分类号： H01L21/76243
摘要： A method to control the quality of a buried oxide region, and to substantially reduce or eliminate deep divots in SOI substrates is provided. Specifically, the inventive method includes the steps of implanting oxygen ions into a surface of a Si-containing substrate; and annealing the Si-containing substrate containing the implanted oxygen ion at a temperature of about 1300° C. or above and in a chlorine-containing ambient so as to form a buried oxide region that electrically isolates a superficial Si-containing layer from a bottom Si-containing layer. The chlorine-containing ambient employed in the annealing step includes oxygen and a chlorine-containing carrier gas such as HCl, methylene chloride, trichloroethylene and trans 1,2-dichloroethane.
摘要翻译：提供了一种控制掩埋氧化物区域的质量并显着减少或消除SOI衬底中的深刻度的方法。具体地，本发明的方法包括将氧离子注入到含Si衬底的表面中的步骤; 以及在约1300℃以上的温度和含氯环境中退火含有所述注入的氧离子的含Si衬底，以便形成掩埋氧化物区域，所述掩埋氧化物区域将表面的含Si层与底部含Si层。在退火步骤中使用的含氯环境包括氧和含氯载体如HCl，二氯甲烷，三氯乙烯和反式1,2-二氯乙烷。

6. 发明授权

US06388327B1 Capping layer for improved silicide formation in narrow semiconductor structures 失效
标题翻译：用于改善窄半导体结构中硅化物形成的封盖层
公开(公告)号：US06388327B1
公开(公告)日：2002-05-14
申请号：US09756938
申请日：2001-01-09
申请人： Kenneth J. Giewont , Stephen Bruce Brodsky , Cyril Cabral, Jr. , Anthony G. Domenicucci , Craig Mitchell Ransom , Yun-Yu Wang , Horatio S. Wildman , Kwong Hon Wong
发明人： Kenneth J. Giewont , Stephen Bruce Brodsky , Cyril Cabral, Jr. , Anthony G. Domenicucci , Craig Mitchell Ransom , Yun-Yu Wang , Horatio S. Wildman , Kwong Hon Wong
IPC分类号： H01L2348
CPC分类号： C23C14/0094 , C23C14/0641 , H01L21/28052 , H01L21/28518 , H01L21/2855
摘要： A capping layer for a semiconductor structure is described. The capping layer is deposited over a silicide-forming metal and has a composition such that nitrogen diffusion therefrom is insufficient to cause formation of an oxynitride from an oxide layer on the underlying silicon. The capping layer may be a metal layer from which no N diffusion occurs, or one or more layers including Ti and/or TiN arranged so that N atoms do not reach the oxide layer. A method is also described for forming the Ti and TiN layers. It is advantageous to deposit non-stoichiometric TiN deficient in N, by sputtering from a Ti target in a nitrogen flow insufficient to cause formation of a nitride on the target.
摘要翻译：描述了半导体结构的覆盖层。覆盖层沉积在硅化物形成金属上，并且具有使得其中的氮扩散不足以引起下层硅上的氧化物层形成氧氮化物的组成。覆盖层可以是不发生N扩散的金属层，或者包括Ti和/或TiN的一个或多个层，以使得N原子不到达氧化物层。还描述了形成Ti和TiN层的方法。通过在不足以引起目标上形成氮化物的氮气流中从Ti靶溅射而在N中沉积非化学计量的TiN是有利的。

7. 发明授权

US07015140B2 Selective salicidation methods 失效
标题翻译：选择性盐化方法
公开(公告)号：US07015140B2
公开(公告)日：2006-03-21
申请号：US10710131
申请日：2004-06-21
申请人： Russell H. Arndt , Kenneth J. Giewont , Kevin E. Mello , M. Dean Sciacca
发明人： Russell H. Arndt , Kenneth J. Giewont , Kevin E. Mello , M. Dean Sciacca
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/823835
摘要： Methods for selective salicidation of a semiconductor device. The invention implements a chemical surface pretreatment by immersion in ozonated water H2O prior to metal deposition. The pretreatment forms an interfacial layer that prevents salicidation over an n-type structure. As a result, the invention does not add any additional process steps to the conventional salicidation processing.
摘要翻译：半导体器件选择性腐蚀的方法。本发明在金属沉积之前通过浸没在臭氧水H 2 O 2中实现化学表面预处理。预处理形成了防止n型结构上的水解的界面层。结果，本发明不对常规的盐化处理添加任何额外的方法步骤。

8. 发明授权

US06967376B2 Divot reduction in SIMOX layers 失效
标题翻译：减少SIMOX层的减少
公开(公告)号：US06967376B2
公开(公告)日：2005-11-22
申请号：US10832215
申请日：2004-04-26
申请人： Stephen R. Fox , Neena Garg , Kenneth J. Giewont , Junedong Lee , Devendra K. Sadana
发明人： Stephen R. Fox , Neena Garg , Kenneth J. Giewont , Junedong Lee , Devendra K. Sadana
IPC分类号： H01L21/762 , H01L27/01 , H01L21/20 , H01L21/265 , H01L29/00
CPC分类号： H01L21/76243
摘要： A method of fabricating a silicon-on-insulator (SOI) having a superficial Si-containing layer that has a reduced number of tile and divot defects is provided. The method includes the steps of: implanting oxygen ions into a surface of a Si-containing substrate, the implanted oxygen ions having a concentration sufficient to form a buried oxide region during a subsequent annealing step; and annealing the substrate containing implanted oxygen ions under conditions wherein the implanted oxygen ions form a buried oxide region which electrically isolates a superficial Si-containing layer from a bottom Si-containing layer. Moreover, the annealing conditions employed are capable of reducing the number of tile or divot defects present in the superficial Si-containing layer so as to allow optical detection of any other defect that has a lower density than the tile or divot defect. The present invention also relates to the SOI substrate that is produced using the inventive method.
摘要翻译：提供了一种制造具有减少数量的瓦和凹陷缺陷的具有表面含Si层的绝缘体上硅（SOI）的方法。该方法包括以下步骤：将氧离子注入到含Si衬底的表面中，注入的氧离子具有足以在随后的退火步骤中形成掩埋氧化物区域的浓度; 以及在其中注入的氧离子形成将表面的含Si层与底部含Si层电隔离的掩埋氧化物区域的条件下退火含有注入的氧离子的衬底。此外，所使用的退火条件能够减少存在于含表面的含Si层中的瓦片或凹陷缺陷的数量，以便允许光学检测具有比瓦或凹陷缺陷更低密度的任何其它缺陷。本发明还涉及使用本发明的方法制造的SOI衬底。

9. 发明授权

US06475893B2 Method for improved fabrication of salicide structures 失效
标题翻译：改善硅化物结构的制造方法
公开(公告)号：US06475893B2
公开(公告)日：2002-11-05
申请号：US09822588
申请日：2001-03-30
申请人： Kenneth J. Giewont , Yun Yu Wang , Russell Arndt , Craig Ransom , Judith Coffin , Anthony Domenicucci , Michael MacDonald , Brian E. Johnson
发明人： Kenneth J. Giewont , Yun Yu Wang , Russell Arndt , Craig Ransom , Judith Coffin , Anthony Domenicucci , Michael MacDonald , Brian E. Johnson
IPC分类号： H01L213205
CPC分类号： H01L21/02054 , H01L21/02063 , H01L21/31111 , H01L29/665
摘要： A method for preparing a semiconductor material for formation of a silicide layer on selected areas thereupon is disclosed. In an exemplary embodiment of the invention, the method includes removing at least one of a nitride and an oxynitride film from the selected areas, removing metallic particles from the selected areas, removing surface particles from the selected areas, removing organics from the selected areas, and removing an oxide layer from the selected areas.
摘要翻译：公开了一种在选定区域上形成硅化物层的半导体材料的方法。在本发明的一个示例性实施例中，该方法包括从所选择的区域去除氮化物和氮氧化物膜中的至少一种，从所选择的区域去除金属颗粒，从所选择的区域去除表面颗粒，从所选择的区域去除有机物，并从所选择的区域去除氧化物层。

10. 发明授权

US5518958A Prevention of agglomeration and inversion in a semiconductor polycide process 失效
标题翻译：防止聚半胱氨酸半导体过程中的聚集和反转
公开(公告)号：US5518958A
公开(公告)日：1996-05-21
申请号：US282681
申请日：1994-07-29
申请人： Kenneth J. Giewont , Anthony J. Yu
发明人： Kenneth J. Giewont , Anthony J. Yu
IPC分类号： H01L21/28 , H01L21/285 , H01L21/324 , H01L21/768 , H01L29/78 , H01L21/44
CPC分类号： H01L21/28061 , H01L21/76838
摘要： Conductors are fabricated by forming a layer of doped polysilicon on a semiconductor substrate, forming a nitrogen-enriched conductive layer on the layer of doped polysilicon, wherein nitrogen contained in the nitrogen-enriched conductive layer provides for improved thermal stability thereof, and patterning the nitrogen-enriched conductive layer and layer of doped polysilicon so as to form the conductors.
摘要翻译：通过在半导体衬底上形成掺杂多晶硅层来形成导体，在掺杂多晶硅层上形成富氮导电层，其中富氮导电层中所含的氮提供了改进的热稳定性，并使氮导电层和掺杂多晶硅层，以形成导体。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式