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1. 发明专利

JP2008042571A Functional module for executing either moving picture coding or decoding and semiconductor integrated circuit containing the same 有权
标题翻译：用于执行移动图像编码或解码的功能模块和包含该模块的半导体集成电路
公开(公告)号：JP2008042571A
公开(公告)日：2008-02-21
申请号：JP2006214869
申请日：2006-08-07
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： IWATA KENICHI , MOCHIZUKI SEIJI , SHIBAYAMA TETSUYA , IZUMIHARA FUMIYUKI , UEDA KOJI , KOBAYASHI YUKIFUMI , NAKADA KEIMEI , HOSOKI KOJI , EHAMA MASAKAZU , YUASA TAKASHI
IPC分类号： H04N19/50 , H04N19/11 , H04N19/42 , H04N19/436 , H04N19/51 , H04N19/593 , H04N19/85
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： PROBLEM TO BE SOLVED: To facilitate the parallel process with a plurality of moving picture parallel processing unit for the intra-frame prediction of the H. 264/AVC. SOLUTION: A function block FB for coding and decoding moving pictures based on the H. 264/AVC comprises two moving picture processing units 2_0, 2_1, and a memory unit LM for storing data related to a process result of a plurality of first macro-blocks MB 600...MB 611 arranged on one line of one picture by the first moving picture processing unit 2_0. Data related to a process result of a plurality of neighboring macro-blocks MB606, MB607, MB608 are transferred from the data stored in the LM to the second moving picture processing unit 2_1, which processes one macro-block MB707 among a plurality of second macro-blocks MB 700...MB 711 arranged on the next line, using the transferred data. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了便于用于H.264 / AVC的帧内预测的多个运动图像并行处理单元的并行处理。解决方案：用于基于H.264 / AVC对运动图像进行编码和解码的功能块FB包括两个运动图像处理单元2_0,2_1和存储单元LM，用于存储与多个由第一运动图像处理单元2_0布置在一个图像的一行上的第一宏块MB 600 ... MB 611。与多个相邻宏块MB606，MB607，MB608的处理结果相关的数据从存储在LM中的数据传送到第二运动图像处理单元2_1，第二运动图像处理单元2_1处理多个第二宏中的一个宏块MB707 - 块MB 700 ... MB 711安排在下一行，使用传输的数据。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2006172256A Information processor 审中-公开
标题翻译：信息处理器
公开(公告)号：JP2006172256A
公开(公告)日：2006-06-29
申请号：JP2004365489
申请日：2004-12-17
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SAEN MAKOTO , UEDA KOJI , YAMAMOTO EIJI
IPC分类号： G06F13/362 , G06F12/00
CPC分类号： G06F13/1605 , G06F13/362
摘要： PROBLEM TO BE SOLVED: To solve a problem that sufficient performance can not be exhibited due to congestion in a specific target resource, in an information processor in which many circuit modules are integrated.
SOLUTION: The information processor is provided with master circuits 401,402, and an arbitration circuit 106 for arbitrating an access right to a bus to which the master circuits 401, 402 are connected. The arbitration circuit 106 has storage parts 407, 413 for storing information showing the priority of the access right, and an arbitration control logic part 408 for arbitrating the access right to the master circuits 401, 402 based on the information. If the priority of the master circuit 401 is higher than the priority of the master circuit 402, and no access request is made from the master circuit 401 and an access request is made from the master circuit 402, the arbitration control logic part 408 permits access from the master circuit 402, and the storage parts 407, 413 do not change the priority of the master circuit 401 and lower the priority of the master circuit 402.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了解决由于特定的目标资源的拥塞而导致在许多电路模块被集成的信息处理器中不能表现出足够的性能的问题。解决方案：信息处理器设有主电路401,402，以及仲裁电路106，用于仲裁与主电路401,402连接的总线的访问权限。仲裁电路106具有用于存储表示访问权限优先级的信息的存储部分407,413，以及用于基于该信息仲裁到主电路401,402的访问权限的仲裁控制逻辑部分408。如果主电路401的优先级高于主电路402的优先级，并且没有从主电路401进行访问请求，并且从主电路402进行访问请求，仲裁控制逻辑部分408允许访问从主电路402和存储部407,413不改变主电路401的优先级并降低主电路402的优先级。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2009237888A Data processor, image coding/decoding device, and data processing system 有权
标题翻译：数据处理器，图像编码/解码设备和数据处理系统
公开(公告)号：JP2009237888A
公开(公告)日：2009-10-15
申请号：JP2008083112
申请日：2008-03-27
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： UEDA KOJI , IWATA KENICHI , MOCHIZUKI SEIJI
IPC分类号： G06F9/50 , H04N19/00 , H04N19/103 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/46 , H04N19/625 , H04N19/70 , H04N19/91
CPC分类号： H04N19/12 , G06F9/50 , H04N19/436
摘要： PROBLEM TO BE SOLVED: To reduce a processing load of an external CPU when a large amount of data is initially set frequently to an image coding/decoding device. SOLUTION: This image encoding/decoding device (data processor) includes a first circuit (103) and a second circuit (102) for providing initial setting to a plurality of image processing modules (processor units), wherein the image encoding/decoding device does not receive information which is initially set to the image processing modules directly from the external CPU, and control information for the initial setting is set to the first circuit from the CPU. The second circuit reads in the initial setting information and setting-target information of the initial setting information from the outside using the control information set in the first circuit and transfers the initial setting information to the image processing module according to the read-in setting-target information. The CPU does not need to set the whole information which is initially set to the image processing modules directly to the image encoding/decoding device, and also does not need to set both a transfer source address and a transfer destination address which are required in such a case of utilizing DMA transfer. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：当对图像编码/解码装置最初频繁地设定大量的数据时，减少外部CPU的处理负荷。解决方案：该图像编码/解码装置（数据处理器）包括用于向多个图像处理模块（处理器单元）提供初始设置的第一电路（103）和第二电路（102），其中图像编码/ 解码装置不直接从外部CPU接收初始设定为图像处理模块的信息，并且从CPU向第一电路设定用于初始设定的控制信息。第二电路使用在第一电路中设置的控制信息从外部读入初始设置信息和初始设置信息的设置目标信息，并根据读入设置将初始设置信息传送到图像处理模块，目标信息。 CPU不需要将初始设置为图像处理模块的整个信息直接设置到图像编码/解码装置，也不需要设置传送源地址和传送目的地地址利用DMA传输的情况。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2008003708A Image processing engine and image processing system including the same 有权
标题翻译：图像处理发动机和图像处理系统，包括它们
公开(公告)号：JP2008003708A
公开(公告)日：2008-01-10
申请号：JP2006170382
申请日：2006-06-20
申请人： Hitachi Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立製作所
发明人： HOSOKI KOJI , EHAMA MASAKAZU , NAKADA KEIMEI , IWATA KENICHI , MOCHIZUKI SEIJI , YUASA TAKASHI , KOBAYASHI YUKIFUMI , SHIBAYAMA TETSUYA , UEDA KOJI , NOBORI MASAKI
IPC分类号： G06F9/34 , G06F9/38 , G06F15/80
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30036 , G06F9/30087
摘要： PROBLEM TO BE SOLVED: To resolve the problem that the power consumption is increased by occurrence of an instruction memory read at every cycle because of supply of one or more instructions in one cycle with respect to instructions issued from a CPU and is increased by the occurrence of simultaneous access of instruction memories at every cycle because of the increase in number of instruction memories for a multiprocessor configuration.
SOLUTION: A means is provided which designates two-dimensional source registers and destination registers to an operand of an instruction, and an operation using a plurality of source registers is executed in a plurality of cycles to obtain a plurality of destinations. In an instruction to obtain destinations by using a plurality of source registers and consuming a plurality of cycles, a data rounding computing unit is connected to the last step of a pipeline. Furthermore, a plurality of CPUs are connected in series and use shared instruction memories in common. In this case, a field for controlling synchronization between adjacent CPUs is provided in an instruction operand of each CPU, whereby synchronization control is performed.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：解决由于在每个周期读取指令存储器而产生的功耗增加的问题，因为相对于从CPU发出的指令在一个周期内提供一个或多个指令并增加由于多处理器配置的指令存储器数量的增加，在每个周期的同时存取指令存储器的发生。解决方案：提供一种将二维源寄存器和目标寄存器指定到指令的操作数的装置，并且以多个周期执行使用多个源寄存器的操作以获得多个目的地。在通过使用多个源寄存器并消耗多个周期来获取目的地的指令中，数据舍入计算单元连接到流水线的最后一个步骤。此外，多个CPU串联连接并共同使用共享指令存储器。在这种情况下，在每个CPU的指令操作数中提供用于控制相邻CPU之间的同步的字段，由此执行同步控制。版权所有（C）2008，JPO＆INPIT

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