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1. 发明专利

JP2008003708A Image processing engine and image processing system including the same 有权
标题翻译：图像处理发动机和图像处理系统，包括它们
公开(公告)号：JP2008003708A
公开(公告)日：2008-01-10
申请号：JP2006170382
申请日：2006-06-20
申请人： Hitachi Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立製作所
发明人： HOSOKI KOJI , EHAMA MASAKAZU , NAKADA KEIMEI , IWATA KENICHI , MOCHIZUKI SEIJI , YUASA TAKASHI , KOBAYASHI YUKIFUMI , SHIBAYAMA TETSUYA , UEDA KOJI , NOBORI MASAKI
IPC分类号： G06F9/34 , G06F9/38 , G06F15/80
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30036 , G06F9/30087
摘要： PROBLEM TO BE SOLVED: To resolve the problem that the power consumption is increased by occurrence of an instruction memory read at every cycle because of supply of one or more instructions in one cycle with respect to instructions issued from a CPU and is increased by the occurrence of simultaneous access of instruction memories at every cycle because of the increase in number of instruction memories for a multiprocessor configuration.
SOLUTION: A means is provided which designates two-dimensional source registers and destination registers to an operand of an instruction, and an operation using a plurality of source registers is executed in a plurality of cycles to obtain a plurality of destinations. In an instruction to obtain destinations by using a plurality of source registers and consuming a plurality of cycles, a data rounding computing unit is connected to the last step of a pipeline. Furthermore, a plurality of CPUs are connected in series and use shared instruction memories in common. In this case, a field for controlling synchronization between adjacent CPUs is provided in an instruction operand of each CPU, whereby synchronization control is performed.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：解决由于在每个周期读取指令存储器而产生的功耗增加的问题，因为相对于从CPU发出的指令在一个周期内提供一个或多个指令并增加由于多处理器配置的指令存储器数量的增加，在每个周期的同时存取指令存储器的发生。解决方案：提供一种将二维源寄存器和目标寄存器指定到指令的操作数的装置，并且以多个周期执行使用多个源寄存器的操作以获得多个目的地。在通过使用多个源寄存器并消耗多个周期来获取目的地的指令中，数据舍入计算单元连接到流水线的最后一个步骤。此外，多个CPU串联连接并共同使用共享指令存储器。在这种情况下，在每个CPU的指令操作数中提供用于控制相邻CPU之间的同步的字段，由此执行同步控制。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2008042571A Functional module for executing either moving picture coding or decoding and semiconductor integrated circuit containing the same 有权
标题翻译：用于执行移动图像编码或解码的功能模块和包含该模块的半导体集成电路
公开(公告)号：JP2008042571A
公开(公告)日：2008-02-21
申请号：JP2006214869
申请日：2006-08-07
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： IWATA KENICHI , MOCHIZUKI SEIJI , SHIBAYAMA TETSUYA , IZUMIHARA FUMIYUKI , UEDA KOJI , KOBAYASHI YUKIFUMI , NAKADA KEIMEI , HOSOKI KOJI , EHAMA MASAKAZU , YUASA TAKASHI
IPC分类号： H04N19/50 , H04N19/11 , H04N19/42 , H04N19/436 , H04N19/51 , H04N19/593 , H04N19/85
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： PROBLEM TO BE SOLVED: To facilitate the parallel process with a plurality of moving picture parallel processing unit for the intra-frame prediction of the H. 264/AVC. SOLUTION: A function block FB for coding and decoding moving pictures based on the H. 264/AVC comprises two moving picture processing units 2_0, 2_1, and a memory unit LM for storing data related to a process result of a plurality of first macro-blocks MB 600...MB 611 arranged on one line of one picture by the first moving picture processing unit 2_0. Data related to a process result of a plurality of neighboring macro-blocks MB606, MB607, MB608 are transferred from the data stored in the LM to the second moving picture processing unit 2_1, which processes one macro-block MB707 among a plurality of second macro-blocks MB 700...MB 711 arranged on the next line, using the transferred data. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了便于用于H.264 / AVC的帧内预测的多个运动图像并行处理单元的并行处理。解决方案：用于基于H.264 / AVC对运动图像进行编码和解码的功能块FB包括两个运动图像处理单元2_0,2_1和存储单元LM，用于存储与多个由第一运动图像处理单元2_0布置在一个图像的一行上的第一宏块MB 600 ... MB 611。与多个相邻宏块MB606，MB607，MB608的处理结果相关的数据从存储在LM中的数据传送到第二运动图像处理单元2_1，第二运动图像处理单元2_1处理多个第二宏中的一个宏块MB707 - 块MB 700 ... MB 711安排在下一行，使用传输的数据。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2006304102A Image coding unit and image coding method 审中-公开
标题翻译：图像编码单元和图像编码方法
公开(公告)号：JP2006304102A
公开(公告)日：2006-11-02
申请号：JP2005125558
申请日：2005-04-22
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SHIBAYAMA TETSUYA
IPC分类号： H04N19/50 , H04N19/102 , H04N19/11 , H04N19/134 , H04N19/136 , H04N19/137 , H04N19/176 , H04N19/196 , H04N19/503 , H04N19/593 , H04N19/60 , H04N19/61 , H04N19/91
CPC分类号： H04N19/11 , H04N19/176 , H04N19/61
摘要： PROBLEM TO BE SOLVED: To provide an image coding unit and an image coding method whereby high speed processing and high image quality can be realized in spite of a simple configuration. SOLUTION: In the case of coding sub macroblocks resulting from dividing a coding target macro block into a plurality of divisions, the image coding unit uses coded image data of a concerned sub macroblock and sub macroblocks adjacent thereto to produce tentative prediction image data formed by a plurality of ways, and generates an in-frame prediction mode determining information for selecting one set of most proper tentative prediction image data from the tentative prediction image data obtained by the plural ways. The image coding unit uses reference image data of the adjacent sub macroblocks according to the prediction mode determining information, produces true prediction image data by means of an in-frame prediction arithmetic operation, and codes a difference from the coded image data. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种图像编码单元和图像编码方法，其中尽管配置简单，但可以实现高速处理和高图像质量。解码：在将编码对象宏块分割为多个分割而得到的子宏块的编码的情况下，图像编码部使用相关子宏块的编码图像数据和与其相邻的子宏块来生成临时预测图像数据通过多种方式形成，并且从通过多种方式获得的临时预测图像数据生成用于从一组最适合的临时预测图像数据中选择的帧内预测模式确定信息。图像编码单元根据预测模式确定信息使用相邻子宏块的参考图像数据，通过帧内预测算术运算产生真实预测图像数据，并对编码图像数据进行编码。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2002261785A SERIAL BUS PROCESSING METHOD AND DEVICE 失效
公开(公告)号：JP2002261785A
公开(公告)日：2002-09-13
申请号：JP2001057901
申请日：2001-03-02
申请人： HITACHI LTD
发明人： HORI JINICHI , OISHI TOSHIHISA , SHIBAYAMA TETSUYA , KATAOKA TOMOHIRO
IPC分类号： G06F13/38 , H04L12/44 , H04L29/14
摘要： PROBLEM TO BE SOLVED: To provide a serial bus processing method and a serial bus-processing device for normally transmitting or receiving data by avoiding loop connection by automatically recognizing the loop connection. SOLUTION: In the serial bus processing method in the serial bus processing device, loop connection that is composed in a serial bus is detected, according to steps S11-S18 to automatically avoid the loop connection, a timer value having a random value is set according to the number of ports that cannot be recognized each node, when detecting the loop connection, and a port is made invalid and a cable is disconnected virtually when the set timer value is reached, thus composing a new bus topology automatically.

5. 发明专利

JP2003244128A SEMICONDUCTOR FOR ENCRYPTION DECODING COMMUNICATION AND RECORDING/REPRODUCING APPARATUS 审中-公开
公开(公告)号：JP2003244128A
公开(公告)日：2003-08-29
申请号：JP2002044281
申请日：2002-02-21
申请人： HITACHI LTD
发明人： TOZAWA ATSUSHI , NOGAMI HIROSHI , SHIBAYAMA TETSUYA , KATAOKA TOMOHIRO , FUJIO HIROSHI
IPC分类号： H04L9/10 , G11B20/00 , H04L29/06 , H04N5/765 , H04N5/775 , H04N5/781 , H04N5/913 , H04N9/804
摘要： PROBLEM TO BE SOLVED: To equip a cipher processing circuit for an IEEE 1394 and the cipher processing circuit for recording in a device necessary for encrypting when recording contents on a media on a recording/reproducing apparatus with 1394 bus interface, and to solve a problem that it is difficult to control viewers of the contents recorded on the media because the contents are recorded en clair when recording the contents on a portable recording media. SOLUTION: A semiconductor for encryption decoding communication incorporated an encryption decoding circuit for IEEE 1394 is provided with a plurality of external interfaces. The encryption decoding circuit inside of the semiconductor for encryption decoding communication can be used as a cipher processing circuit for recording when an apparatus independently operates. COPYRIGHT: (C)2003,JPO

6. 发明专利

JP2001339383A SEMICONDUCTOR DEVICE FOR AUTHENTICATION COMMUNICATION 失效
公开(公告)号：JP2001339383A
公开(公告)日：2001-12-07
申请号：JP2000158770
申请日：2000-05-29
申请人： HITACHI LTD
发明人： OISHI TOSHIHISA , TOZAWA ATSUSHI , SHIBAYAMA TETSUYA , HAMADA MASATO
IPC分类号： G06F12/14 , G06F1/00 , G06F21/24 , H04L9/10 , H04L29/06 , H04N5/765 , H04N5/77 , H04N5/775 , H04N5/913
摘要： PROBLEM TO BE SOLVED: To solve problems in the conventional semiconductor device for authentication communication that it has possibility of breaking the contrivance of illegal copy prevention by connecting a probe of a logic analyzer to a CPU bus so as to steal the authentication process and to analyze it in order to break the technology for preventing illegal copy and has the possibility of remodeling an electronic device for setting a falsified encryption key to the CPU bus. SOLUTION: A main processing section that generates a key code according to a prescribed algorithm, decides approval/disapproval of transmission/reception of data to/from an external device and conducts communication control, an encryption section that uses a key code generated by the main processing section to conduct encryption and decoding of transmission reception data and an interface section that conducts communication with a high-order layer or a low-order layer according to a prescribed protocol are formed on one semiconductor chip so that the encryption key in the encryption process and the authentication process is hardly stolen from the outside of the device.

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