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1. 发明专利

JP2008003708A Image processing engine and image processing system including the same 有权
标题翻译：图像处理发动机和图像处理系统，包括它们
公开(公告)号：JP2008003708A
公开(公告)日：2008-01-10
申请号：JP2006170382
申请日：2006-06-20
申请人： Hitachi Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立製作所
发明人： HOSOKI KOJI , EHAMA MASAKAZU , NAKADA KEIMEI , IWATA KENICHI , MOCHIZUKI SEIJI , YUASA TAKASHI , KOBAYASHI YUKIFUMI , SHIBAYAMA TETSUYA , UEDA KOJI , NOBORI MASAKI
IPC分类号： G06F9/34 , G06F9/38 , G06F15/80
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30036 , G06F9/30087
摘要： PROBLEM TO BE SOLVED: To resolve the problem that the power consumption is increased by occurrence of an instruction memory read at every cycle because of supply of one or more instructions in one cycle with respect to instructions issued from a CPU and is increased by the occurrence of simultaneous access of instruction memories at every cycle because of the increase in number of instruction memories for a multiprocessor configuration.
SOLUTION: A means is provided which designates two-dimensional source registers and destination registers to an operand of an instruction, and an operation using a plurality of source registers is executed in a plurality of cycles to obtain a plurality of destinations. In an instruction to obtain destinations by using a plurality of source registers and consuming a plurality of cycles, a data rounding computing unit is connected to the last step of a pipeline. Furthermore, a plurality of CPUs are connected in series and use shared instruction memories in common. In this case, a field for controlling synchronization between adjacent CPUs is provided in an instruction operand of each CPU, whereby synchronization control is performed.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：解决由于在每个周期读取指令存储器而产生的功耗增加的问题，因为相对于从CPU发出的指令在一个周期内提供一个或多个指令并增加由于多处理器配置的指令存储器数量的增加，在每个周期的同时存取指令存储器的发生。解决方案：提供一种将二维源寄存器和目标寄存器指定到指令的操作数的装置，并且以多个周期执行使用多个源寄存器的操作以获得多个目的地。在通过使用多个源寄存器并消耗多个周期来获取目的地的指令中，数据舍入计算单元连接到流水线的最后一个步骤。此外，多个CPU串联连接并共同使用共享指令存储器。在这种情况下，在每个CPU的指令操作数中提供用于控制相邻CPU之间的同步的字段，由此执行同步控制。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2004280623A Security system 有权
公开(公告)号：JP2004280623A
公开(公告)日：2004-10-07
申请号：JP2003072919
申请日：2003-03-18
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： EHAMA MASAKAZU , TANAKA KAZUHIKO , HOSOKI KOJI , NAKADA KEIMEI
IPC分类号： G06F12/14 , G06F12/08 , G06F12/10
CPC分类号： G06F12/1441 , G06F12/1027 , G06F12/1425
摘要： PROBLEM TO BE SOLVED: To solve a problem that possibility exists that confidential data including an encryption key or the like are read, and developed software is copied since the read or the alteration of a register in a processor or a local memory are possible through an external bus. SOLUTION: A media processor having the bus connected to an external device permits all accesses from other devices connected to the external bus. Therefore, the bus interface portion of the media processor is provided with a TLB (Translation Look-aside Buffer) to protect confidential items in the processor. The TLB is rewritable only from the processor. The TLB determines whether an externally accessed address is accessible. When access permission is described in the TLB, the access to the media processor is generated. If not, a request is abandoned. COPYRIGHT: (C)2005,JPO&NCIPI

3. 发明专利

JP2009015637A Computational unit and image filtering apparatus 审中-公开
标题翻译：计算单元和图像滤波装置
公开(公告)号：JP2009015637A
公开(公告)日：2009-01-22
申请号：JP2007177299
申请日：2007-07-05
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： EHAMA MASAKAZU , HOSOKI KOJI , MOCHIZUKI SEIJI
IPC分类号： G06T5/20
CPC分类号： G06T1/20 , G06T7/223 , G06T2207/10016 , G06T2207/20021
摘要： PROBLEM TO BE SOLVED: To provide a processor capable of executing filtering processing at a high speed. SOLUTION: The computational unit relating to this invention is provided with a computing unit 201 for executing the filtering processing. Data supply to the computing unit 201 is performed in an internal register 100 comprising a flip-flop. Data read from the internal register 100 are output to a shift register 200 and the data are supplied to the computing unit 201 for each cycle. Also, a mechanism for changing the computing direction of a filter according to a motion vector is provided, and by executing horizontal filtering and vertical filtering by the same instruction, performance decline due to a branch instruction or the like is prevented. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供能够高速执行滤波处理的处理器。解决方案：涉及本发明的计算单元设置有用于执行滤波处理的计算单元201。在包括触发器的内部寄存器100中执行向计算单元201的数据提供。从内部寄存器100读取的数据被输出到移位寄存器200，并且每个周期将数据提供给计算单元201。此外，提供了用于根据运动矢量改变滤波器的计算方向的机构，并且通过执行相同指令的水平滤波和垂直滤波，防止由于分支指令等导致的性能下降。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2008262437A Processor system and exception handling method 审中-公开
标题翻译：处理器系统和异常处理方法
公开(公告)号：JP2008262437A
公开(公告)日：2008-10-30
申请号：JP2007105467
申请日：2007-04-13
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： YUASA TAKASHI , NAKADA KEIMEI , HOSOKI KOJI , EHAMA MASAKAZU , IZUMIHARA FUMIYUKI , AKIE KAZUSHI
IPC分类号： G06F9/38 , G06F9/42 , G06F9/48 , G06F15/78
CPC分类号： G06F11/0793 , G06F9/30054 , G06F9/3861 , G06F9/3885 , G06F9/4812 , G06F11/0721 , G06F2209/481
摘要： PROBLEM TO BE SOLVED: To provide a microprocessor accompanied by a coprocessor which does not save a command address when an error occurs and execution command return control after completion of error processing.
SOLUTION: In a processor system, when an error detection unit 120 detects an error, it outputs an error signal to an interruption control unit 64. The control unit 64 outputs a value in an error address register 61 and a control signal to a program counter control unit 20, and achieves branch processing due to an error interruption by rewriting a value of a program counter 21 into the value in the register 61. When the error is detected, the system does not perform processing to save the value of the counter 21 when the error occurs, and is not provided with a control circuit for returning to a specified save register and to the command address at error occurrence after error processing.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一个伴随着协处理器的微处理器，当发生错误时不保存命令地址，并且在完成错误处理之后执行命令返回控制。解决方案：在处理器系统中，当错误检测单元120检测到错误时，它将错误信号输出到中断控制单元64.控制单元64将错误地址寄存器61中的值和控制信号输出到程序计数器控制单元20，通过将程序计数器21的值重写为寄存器61的值，由于错误中断而实现分支处理。当检测到错误时，系统不执行保存错误发生时的计数器21，并且在错误处理之后没有设置用于返回到指定的保存寄存器的控制电路和错误发生时的命令地址。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2008042571A Functional module for executing either moving picture coding or decoding and semiconductor integrated circuit containing the same 有权
标题翻译：用于执行移动图像编码或解码的功能模块和包含该模块的半导体集成电路
公开(公告)号：JP2008042571A
公开(公告)日：2008-02-21
申请号：JP2006214869
申请日：2006-08-07
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： IWATA KENICHI , MOCHIZUKI SEIJI , SHIBAYAMA TETSUYA , IZUMIHARA FUMIYUKI , UEDA KOJI , KOBAYASHI YUKIFUMI , NAKADA KEIMEI , HOSOKI KOJI , EHAMA MASAKAZU , YUASA TAKASHI
IPC分类号： H04N19/50 , H04N19/11 , H04N19/42 , H04N19/436 , H04N19/51 , H04N19/593 , H04N19/85
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： PROBLEM TO BE SOLVED: To facilitate the parallel process with a plurality of moving picture parallel processing unit for the intra-frame prediction of the H. 264/AVC. SOLUTION: A function block FB for coding and decoding moving pictures based on the H. 264/AVC comprises two moving picture processing units 2_0, 2_1, and a memory unit LM for storing data related to a process result of a plurality of first macro-blocks MB 600...MB 611 arranged on one line of one picture by the first moving picture processing unit 2_0. Data related to a process result of a plurality of neighboring macro-blocks MB606, MB607, MB608 are transferred from the data stored in the LM to the second moving picture processing unit 2_1, which processes one macro-block MB707 among a plurality of second macro-blocks MB 700...MB 711 arranged on the next line, using the transferred data. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了便于用于H.264 / AVC的帧内预测的多个运动图像并行处理单元的并行处理。解决方案：用于基于H.264 / AVC对运动图像进行编码和解码的功能块FB包括两个运动图像处理单元2_0,2_1和存储单元LM，用于存储与多个由第一运动图像处理单元2_0布置在一个图像的一行上的第一宏块MB 600 ... MB 611。与多个相邻宏块MB606，MB607，MB608的处理结果相关的数据从存储在LM中的数据传送到第二运动图像处理单元2_1，第二运动图像处理单元2_1处理多个第二宏中的一个宏块MB707 - 块MB 700 ... MB 711安排在下一行，使用传输的数据。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2004179810A Image encoder 审中-公开
标题翻译：图像编码器
公开(公告)号：JP2004179810A
公开(公告)日：2004-06-24
申请号：JP2002341662
申请日：2002-11-26
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： HOSOKI KOJI , NISHIOKA KIYOKAZU , FUJIKAWA YOSHIBUMI , EHAMA MASAKAZU
IPC分类号： H04N19/50 , H03M7/36 , H04N19/105 , H04N19/112 , H04N19/42 , H04N19/423 , H04N19/503 , H04N19/51 , H04N19/577 , H04N19/61 , H04N19/625 , H04N19/85 , H04N7/32
摘要： PROBLEM TO BE SOLVED: To provide an image encoder for performing motion searching processing in compliance with the MPEG2 and MPEG4 standards with a small quantity of hardware.
SOLUTION: The image encoder includes: an error accumulating arithmetic unit capable of calculating the absolute difference sum of at least one field block comprising 8 lateral pixels and 4 longitudinal pixels in order to perform the motion searching processing for both the MPEG2 and MPEG4 with one hardware resource; and a means that combines the absolute difference sum and sums up the combined sums so as to calculate an error and a motion vector with respect to frame prediction in the MPEG2, an error and a motion vector with respect to field prediction, an error and a motion vector with respect to 16×8 field prediction, and an error and a motion vector with respect to 4MV prediction in parallel, and stores minimum values of the respective errors and the motion vectors.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种图像编码器，用于以少量的硬件来执行符合MPEG2和MPEG4标准的运动搜索处理。解决方案：图像编码器包括：误差累积算术单元，其能够计算包括8个横向像素和4个纵向像素的至少一个场块的绝对差值和，以执行MPEG2和MPEG4两者的运动搜索处理一个硬件资源; 以及组合绝对差值和并将合并和相加的方法，以便计算相对于MPEG2中的帧预测的误差和运动矢量，相对于场预测的误差和运动矢量，误差和相对于16×8场预测的运动矢量，以及相对于并联的4MV预测的误差和运动矢量，并存储各个误差和运动矢量的最小值。版权所有（C）2004，JPO

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