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1. 发明授权

US09195464B2 Tracking written addresses of a shared memory of a multi-core processor 有权
标题翻译：跟踪多核处理器的共享内存的写入地址
公开(公告)号：US09195464B2
公开(公告)日：2015-11-24
申请号：US13316145
申请日：2011-12-09
申请人： David Sonnier , Chris Randall Stone , Charles Edward Peet, Jr.
发明人： David Sonnier , Chris Randall Stone , Charles Edward Peet, Jr.
IPC分类号： G06F9/46 , G06F9/54 , G06F9/38 , H04L12/933 , H04L12/931 , G06F12/08
CPC分类号： G06F9/3834 , G06F12/0811 , G06F12/084 , G06F2212/301 , H04L49/101 , H04L49/109 , H04L49/506
摘要： Described embodiments provide a method of controlling processing flow in a network processor having one or more processing modules. A given one of the processing modules loads a script into a compute engine. The script includes instructions for the compute engine. The given one of the processing modules loads a register file into the compute engine. The register file includes operands for the instructions of the loaded script. A tracking vector of the compute engine is initialized to a default value, and the compute engine executes the instructions of the loaded script based on the operands of the loaded register file. The compute engine updates corresponding portions of the register file with updated data corresponding to the executed script. The tracking vector tracks the updated portions of the register file. The compute engine provides the tracking vector and the updated register file to the given one of the processing modules.
摘要翻译：所描述的实施例提供了一种控制具有一个或多个处理模块的网络处理器中的处理流程的方法。给定的一个处理模块将脚本加载到计算引擎中。该脚本包括计算引擎的说明。给定的一个处理模块将一个寄存器文件加载到计算引擎中。寄存器文件包括用于加载脚本的指令的操作数。计算引擎的跟踪向量被初始化为默认值，并且计算引擎基于加载的寄存器文件的操作数来执行加载脚本的指令。计算引擎使用对应于执行脚本的更新数据更新寄存器文件的相应部分。跟踪向量跟踪寄存器文件的更新部分。计算引擎将跟踪向量和更新的寄存器文件提供给给定的一个处理模块。

2. 发明申请

US20120084498A1 TRACKING WRITTEN ADDRESSES OF A SHARED MEMORY OF A MULTI-CORE PROCESSOR 有权
标题翻译：跟踪多核处理器共享存储器的书写地址
公开(公告)号：US20120084498A1
公开(公告)日：2012-04-05
申请号：US13316145
申请日：2011-12-09
申请人： David Sonnier , Chris Randall Stone , Charles Edwards Peet, JR.
发明人： David Sonnier , Chris Randall Stone , Charles Edwards Peet, JR.
IPC分类号： G06F12/00 , G06F12/08 , G06F9/30
CPC分类号： G06F9/3834 , G06F12/0811 , G06F12/084 , G06F2212/301 , H04L49/101 , H04L49/109 , H04L49/506
摘要： Described embodiments provide a method of controlling processing flow in a network processor having one or more processing modules. A given one of the processing modules loads a script into a compute engine. The script includes instructions for the compute engine. The given one of the processing modules loads a register file into the compute engine. The register file includes operands for the instructions of the loaded script. A tracking vector of the compute engine is initialized to a default value, and the compute engine executes the instructions of the loaded script based on the operands of the loaded register file. The compute engine updates corresponding portions of the register file with updated data corresponding to the executed script. The tracking vector tracks the updated portions of the register file. The compute engine provides the tracking vector and the updated register file to the given one of the processing modules.
摘要翻译：所描述的实施例提供了一种控制具有一个或多个处理模块的网络处理器中的处理流程的方法。给定的一个处理模块将脚本加载到计算引擎中。该脚本包括计算引擎的说明。给定的一个处理模块将一个寄存器文件加载到计算引擎中。寄存器文件包括用于加载脚本的指令的操作数。计算引擎的跟踪向量被初始化为默认值，并且计算引擎基于加载的寄存器文件的操作数来执行加载脚本的指令。计算引擎使用对应于执行脚本的更新数据更新寄存器文件的相应部分。跟踪向量跟踪寄存器文件的更新部分。计算引擎将跟踪向量和更新的寄存器文件提供给给定的一个处理模块。

3. 发明授权

US06516420B1 Data synchronizer using a parallel handshaking pipeline wherein validity indicators generate and send acknowledgement signals to a different clock domain 有权
标题翻译：使用并行握手管道的数据同步器，其中有效性指示符生成并向不同的时钟域发送确认信号
公开(公告)号：US06516420B1
公开(公告)日：2003-02-04
申请号：US09426265
申请日：1999-10-25
申请人： Srinath Audityan , Chris Randall Stone , Ritesh Radheshyam Agrawal
发明人： Srinath Audityan , Chris Randall Stone , Ritesh Radheshyam Agrawal
IPC分类号： G06F1342
CPC分类号： G06F5/12 , H04L7/02
摘要： A data synchronizer transfers information across an asynchronous interface by using system domain and core domain logic on either side of the asynchronous interface. Information registers receive data beats from a data bus coupled to an external system. Each data beat is loaded into the registers in sequential order. A corresponding system valid bit is provided for each register and is set when the corresponding register is loaded. In the core domain, a corresponding set of core valid bit registers is set in response to the system valid bit registers being set. A data sampler monitors the core valid bits in sequential order and controls a multiplexor to select a corresponding one of the registers that contains valid data. The data sampler resets the core valid bits which in-turn reset the system valid bits to signal the completion of a data transfer across the asynchronous interface.
摘要翻译：数据同步器通过使用异步接口任意一侧的系统域和核心域逻辑跨异步接口传输信息。信息寄存器从耦合到外部系统的数据总线接收数据节拍。每个数据节拍按顺序加载到寄存器中。为每个寄存器提供相应的系统有效位，并在对应的寄存器加载时置1。在核心域中，响应于设置了系统有效位寄存器，设置相应的一组核心有效位寄存器。数据采样器按顺序监视核心有效位，并控制多路复用器选择包含有效数据的相应的一个寄存器。数据采样器将复位核心有效位，从而重置系统有效位，以通知异步接口数据传输的完成。

4. 发明授权

US06389489B1 Data processing system having a fifo buffer with variable threshold value based on input and output data rates and data block size 有权
标题翻译：数据处理系统具有基于输入和输出数据速率和数据块大小的具有可变阈值的fifo缓冲器
公开(公告)号：US06389489B1
公开(公告)日：2002-05-14
申请号：US09271215
申请日：1999-03-17
申请人： Chris Randall Stone , Ritesh Radheshyam Agrawal
发明人： Chris Randall Stone , Ritesh Radheshyam Agrawal
IPC分类号： G06F1300
CPC分类号： G06F5/12 , G06F2205/108 , G06F2205/126 , G11C19/287
摘要： A data processor (102) includes a first-in, first-out (FIFO) buffer (110) having a variable threshold. The FIFO buffer (110) has a plurality of entries (200) for storing at least a portion of a data block that is to be transmitted through the FIFO buffer (110). To allow data blocks of varying size to be transmitted at different data rates, a variable threshold value for determining a maximum fullness of the FIFO buffer (110) is automatically calculated by the data processor (102) for each data block. This allows the data block to be transmitted through the FIFO buffer (110) as a continuous data stream, without interruption, from the data processor (102) to a data consumer. The variable threshold value is appended to a first entry of the data block along with start bits to indicate a beginning of the data block. The FIFO buffer (110) may include read and write counters (208, 212) and a comparator (210) for comparing a difference between read and write pointers and the variable threshold value.
摘要翻译：数据处理器（102）包括具有可变阈值的先入先出（FIFO）缓冲器（110）。 FIFO缓冲器（110）具有用于存储要通过FIFO缓冲器（110）发送的数据块的至少一部分的多个条目（200）。为了允许以不同数据速率传输不同大小的数据块，用于确定FIFO缓冲器（110）的最大饱和度的可变阈值由数据处理器（102）自动计算用于每个数据块。这允许数据块作为连续数据流通过FIFO缓冲器（110）从数据处理器（102）传输到数据消费者，而不会中断。可变阈值与起始位一起被附加到数据块的第一条目，以指示数据块的开头。 FIFO缓冲器（110）可以包括读取和写入计数器（208,212）和用于比较读取和写入指针之间的差异与可变阈值的比较器（210）。

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