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1. 发明申请

US20110066918A1 SOFT ERROR CORRECTION IN A MEMORY ARRAY AND METHOD THEREOF 有权
标题翻译：存储器阵列中的软错误校正及其方法
公开(公告)号：US20110066918A1
公开(公告)日：2011-03-17
申请号：US12560999
申请日：2009-09-16
申请人： Ravindraraj Ramaraju , David R. Bearden , Troy L. Cooper
发明人： Ravindraraj Ramaraju , David R. Bearden , Troy L. Cooper
IPC分类号： H03M13/07 , G06F11/10
CPC分类号： G06F11/1012
摘要： A memory system includes a memory array. The memory array includes a plurality of storage locations arranged in rows and columns. The memory system includes error correction circuitry that generates correct data bits from data bits of the memory array and error correction bits. The data bits received by the error correction circuitry are divided in subgroups where each subgroup of data bits is used to generate a subgroup of the correct data bits. The subgroups of data bits are stored in a row of the memory array at locations that are interleaved with each other.
摘要翻译：存储器系统包括存储器阵列。存储器阵列包括以行和列布置的多个存储位置。存储器系统包括纠错电路，其从存储器阵列的数据位和纠错位产生正确的数据位。由纠错电路接收的数据位被划分成子组，其中每个子组的数据位用于产生正确数据位的子组。数据位的子组在相互交错的位置存储在存储器阵列的一行中。

2. 发明授权

US08489906B2 Data processor having multiple low power modes 有权
标题翻译：具有多个低功率模式的数据处理器
公开(公告)号：US08489906B2
公开(公告)日：2013-07-16
申请号：US12786916
申请日：2010-05-25
申请人： Ravindraraj Ramaraju , David R. Bearden , Troy L. Cooper
发明人： Ravindraraj Ramaraju , David R. Bearden , Troy L. Cooper
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3287 , H03K19/0016 , Y02D10/171
摘要： A processor includes a first virtual terminal, a second virtual terminal, circuitry coupled to the first virtual terminal for providing current to the first virtual terminal, a first regulating transistor coupled between the first virtual terminal and the second virtual terminal, a first disabling transistor coupled in parallel with the first regulating transistor for selectively disabling the first regulating transistor by directly connecting the second virtual terminal to the first virtual terminal, a second regulating transistor coupled between the second virtual terminal and a first power supply voltage terminal, and a second disabling transistor coupled in parallel with the second regulating transistor for selectively disabling the second regulating transistor by directly connecting the second virtual terminal to the first power supply voltage terminal.
摘要翻译：处理器包括第一虚拟终端，第二虚拟终端，耦合到第一虚拟终端的用于向第一虚拟终端提供电流的电路，耦合在第一虚拟终端和第二虚拟终端之间的第一调节晶体管，耦合到第一虚拟终端与第一调节晶体管并联，用于通过将第二虚拟端子直接连接到第一虚拟端子来选择性地禁用第一调节晶体管，耦合在第二虚拟端子和第一电源电压端子之间的第二调节晶体管和第二禁止晶体管与第二调节晶体管并联，用于通过将第二虚拟端子直接连接到第一电源电压端子来选择性地禁用第二调节晶体管。

3. 发明授权

US08365036B2 Soft error correction in a memory array and method thereof 有权
标题翻译：存储器阵列中的软错误校正及其方法
公开(公告)号：US08365036B2
公开(公告)日：2013-01-29
申请号：US12560999
申请日：2009-09-16
申请人： Ravindraraj Ramaraju , David R. Bearden , Troy L. Cooper
发明人： Ravindraraj Ramaraju , David R. Bearden , Troy L. Cooper
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： G06F11/1012
摘要： A memory system includes a memory array. The memory array includes a plurality of storage locations arranged in rows and columns. The memory system includes error correction circuitry that generates correct data bits from data bits of the memory array and error correction bits. The data bits received by the error correction circuitry are divided in subgroups where each subgroup of data bits is used to generate a subgroup of the correct data bits. The subgroups of data bits are stored in a row of the memory array at locations that are interleaved with each other.
摘要翻译：存储器系统包括存储器阵列。存储器阵列包括以行和列布置的多个存储位置。存储器系统包括纠错电路，其从存储器阵列的数据位和纠错位产生正确的数据位。由纠错电路接收的数据位被划分成子组，其中每个子组的数据位用于产生正确数据位的子组。数据位的子组在相互交错的位置存储在存储器阵列的一行中。

4. 发明申请

US20110296211A1 DATA PROCESSOR HAVING MULTIPLE LOW POWER MODES 有权
标题翻译：具有多种低功耗模式的数据处理器
公开(公告)号：US20110296211A1
公开(公告)日：2011-12-01
申请号：US12786916
申请日：2010-05-25
申请人： Ravindraraj Ramaraju , David R. Bearden , Troy L. Cooper
发明人： Ravindraraj Ramaraju , David R. Bearden , Troy L. Cooper
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3203 , G06F1/3287 , H03K19/0016 , Y02D10/171
摘要： A processor includes a first virtual terminal, a second virtual terminal, circuitry coupled to the first virtual terminal for providing current to the first virtual terminal, a first regulating transistor coupled between the first virtual terminal and the second virtual terminal, a first disabling transistor coupled in parallel with the first regulating transistor for selectively disabling the first regulating transistor by directly connecting the second virtual terminal to the first virtual terminal, a second regulating transistor coupled between the second virtual terminal and a first power supply voltage terminal, and a second disabling transistor coupled in parallel with the second regulating transistor for selectively disabling the second regulating transistor by directly connecting the second virtual terminal to the first power supply voltage terminal.
摘要翻译：处理器包括第一虚拟终端，第二虚拟终端，耦合到第一虚拟终端的用于向第一虚拟终端提供电流的电路，耦合在第一虚拟终端和第二虚拟终端之间的第一调节晶体管，耦合到第一虚拟终端与第一调节晶体管并联，用于通过将第二虚拟端子直接连接到第一虚拟端子来选择性地禁用第一调节晶体管，耦合在第二虚拟端子和第一电源电压端子之间的第二调节晶体管和第二禁止晶体管与第二调节晶体管并联，用于通过将第二虚拟端子直接连接到第一电源电压端子来选择性地禁用第二调节晶体管。

5. 发明授权

US07215188B2 Integrated circuit having a low power mode and method therefor 有权
标题翻译：具有低功率模式的集成电路及其方法
公开(公告)号：US07215188B2
公开(公告)日：2007-05-08
申请号：US11065796
申请日：2005-02-25
申请人： Ravindraraj Ramaraju , David R. Bearden , Troy L. Cooper
发明人： Ravindraraj Ramaraju , David R. Bearden , Troy L. Cooper
IPC分类号： G05F3/02
CPC分类号： H03K19/0016 , H03K3/0375
摘要： An integrated circuit (70) includes a first power supply bus (72) and a second power supply bus (74). The first power supply bus (72) provides a first power supply voltage (VDD) to a first plurality of circuit elements (12 and 76). The second power supply bus (74) provides a second power supply voltage (LVDD) to a second plurality of circuit elements (14), where the second power supply voltage is lower than the first power supply voltage. During a normal operating mode of the integrated circuit (70), the first power supply bus (72) provides the first power supply voltage to the first plurality of circuit elements (12 and 76) and the second power supply voltage is not provided to the second plurality of circuit elements (14). During a low power operating mode, the second power supply bus (74) provides the second power supply voltage to the second plurality of circuit elements (14) and the first power supply voltage is not provided to the first plurality of circuit elements (12 and 76).
摘要翻译：集成电路（70）包括第一电源总线（72）和第二电源总线（74）。第一电源总线（72）向第一多个电路元件（12和76）提供第一电源电压（VDD）。第二电源总线（74）向第二多个电路元件（14）提供第二电源电压（LVDD），其中第二电源电压低于第一电源电压。在集成电路（70）的正常操作模式期间，第一电源总线（72）向第一多个电路元件（12和76）提供第一电源电压，并且第二电源电压不提供给第二多个电路元件（14）。在低功率操作模式期间，第二电源总线（74）向第二多个电路元件（14）提供第二电源电压，并且第一电源电压不提供给第一多个电路元件（12和 76）。

6. 发明授权

US09367475B2 System and method for cache access 有权
标题翻译：用于缓存访问的系统和方法
公开(公告)号：US09367475B2
公开(公告)日：2016-06-14
申请号：US13440728
申请日：2012-04-05
申请人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell
发明人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell
IPC分类号： G06F12/00 , G06F13/00 , G06F12/08 , G06F1/32
CPC分类号： G06F12/0895 , G06F1/3225 , G06F1/3275 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： The rows of a cache are generally maintained in a low power state. In response to a memory access operation, the data processor predicts a plurality of cache rows that may be targeted by the operation, and transitions each of the plurality of cache rows to an active state to prepare them for access. The plurality of cache rows are predicted based on speculatively decoding a portion of a base address and a corresponding portion of an offset without performing a full addition of the portions. Because a full addition is not performed, the speculative decoding can be performed at sufficient speed to allow the set of rows to be transitioned to the active state before full decoding of the memory address is completed. The cache row associated with the memory address is therefore ready for access when decoding is complete, maintaining low latency for cache accesses.
摘要翻译：缓存的行通常维持在低功率状态。响应于存储器访问操作，数据处理器预测可能由操作定向的多个高速缓存行，并且将多个高速缓存行中的每一个转换为活动状态以准备它们进行访问。基于对基本地址的一部分和偏移的对应部分的推测性解码来预测多个高速缓存行，而不执行部分的完全添加。由于没有执行完全相加，所以可以以足够的速度执行推测解码，以便在存储器地址的完全解码完成之前允许该组行转换到活动状态。因此，当解码完成时，与存储器地址相关联的高速缓存行可以进行访问，从而保持高速缓存访问的低延迟。

7. 发明申请

US20120200336A1 ELECTRONIC CIRCUIT HAVING SHARED LEAKAGE CURRENT REDUCTION CIRCUITS 有权
标题翻译：具有共享漏电流减少电路的电子电路
公开(公告)号：US20120200336A1
公开(公告)日：2012-08-09
申请号：US13020565
申请日：2011-02-03
申请人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell , Shayan Zhang
发明人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell , Shayan Zhang
IPC分类号： H03K3/011 , G05F1/10
CPC分类号： H03K19/0008 , H03K19/0016
摘要： An electronic circuit includes a plurality of circuit blocks, a plurality of bias circuits, a switching circuit, and plurality of transistors. The plurality of circuit blocks each includes a high power terminal and a low power terminal. The switching circuit includes a plurality of switches for selectively coupling a bias circuit of the plurality of bias circuits to the low power terminal of a circuit block of the plurality of circuit blocks. Each bias circuit of the plurality of bias circuits is selectively couplable to the low power terminal of each of the plurality of circuit blocks. Each transistor of the plurality of transistors has a first current terminal coupled to a circuit ground terminal, and each transistor of the plurality of transistors has a control terminal for controlling the conductivity of the plurality of the transistors by a bias circuit of the plurality of bias circuits.
摘要翻译：电子电路包括多个电路块，多个偏置电路，开关电路和多个晶体管。多个电路块各自包括高功率端子和低功率端子。开关电路包括多个开关，用于将多个偏置电路的偏置电路选择性地耦合到多个电路块的电路块的低功率端子。多个偏置电路的每个偏置电路可以选择性地耦合到多个电路块中的每一个的低功率端子。多个晶体管的每个晶体管具有耦合到电路接地端子的第一电流端子，并且多个晶体管中的每个晶体管具有控制端子，用于通过多个偏置的偏置电路来控制多个晶体管的导电性电路。

8. 发明授权

US08189408B2 Memory device having shifting capability and method thereof 有权
标题翻译：具有移动能力的存储装置及其方法
公开(公告)号：US08189408B2
公开(公告)日：2012-05-29
申请号：US12620314
申请日：2009-11-17
申请人： Ravi Gupta , David R. Bearden , Ravindraraj Ramaraju
发明人： Ravi Gupta , David R. Bearden , Ravindraraj Ramaraju
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G11C7/1075 , G11C7/18 , G11C19/00 , G11C19/28
摘要： An array of memory bit cells are operable to provide a memory device having data shifting capability, so that data can be flexibly stored and retrieved from the memory device in both parallel and serial fashions. The memory array can thus be used for conventional memory storage operations, and also for operations, such as matrix operations, that provide for the alteration of the arrangement of stored data elements.
摘要翻译：存储器位单元阵列可操作以提供具有数据移位能力的存储器件，从而能够以并行和串行方式从存储器件灵活地存储和检索数据。因此，存储器阵列可以用于常规存储器存储操作，并且还可以用于提供对存储的数据元素的布置的改变的诸如矩阵操作的操作。

9. 发明申请

US20120036398A1 MULTIPLE CORE DATA PROCESSOR WITH USAGE MONITORING 审中-公开
标题翻译：多核心数据处理器使用监控
公开(公告)号：US20120036398A1
公开(公告)日：2012-02-09
申请号：US13272725
申请日：2011-10-13
申请人： William C. Moyer , David R. Bearden , Ravindraraj Ramaraju
发明人： William C. Moyer , David R. Bearden , Ravindraraj Ramaraju
IPC分类号： G06F11/14 , G06F9/312
CPC分类号： G06F9/505 , G06F16/217 , G06F2209/504 , G06F2209/508 , Y02D10/22
摘要： A data processor with a plurality of processor cores. Accumulated usage information of each of the plurality of processor cores is stored in a storage device within the data processor, wherein the accumulated usage information is indicative of accumulated usage of each processor core of the plurality of processor cores. The processor uses the accumulated usage information in selecting processor cores to perform processor operations.
摘要翻译：具有多个处理器核心的数据处理器。多个处理器核心中的每一个的累积使用信息被存储在数据处理器内的存储设备中，其中累积的使用信息指示多个处理器核心的每个处理器核心的累积使用。处理器使用累积的使用信息来选择处理器核心来执行处理器操作。

10. 发明申请

US20120033520A1 MEMORY WITH LOW VOLTAGE MODE OPERATION 有权
标题翻译：低电压模式运行的存储器
公开(公告)号：US20120033520A1
公开(公告)日：2012-02-09
申请号：US12850533
申请日：2010-08-04
申请人： Huy B. Nguyen , Troy L. Cooper , Ravindraraj Ramaraju , Andrew C. Russell
发明人： Huy B. Nguyen , Troy L. Cooper , Ravindraraj Ramaraju , Andrew C. Russell
IPC分类号： G11C5/14
CPC分类号： G11C11/417
摘要： A memory comprising memory cells wherein the memory is configured to operate in a normal voltage mode and a low voltage mode. The method includes during the normal voltage mode, operating the memory cells at a first voltage across each of the memory cells. The method further includes upon transitioning from the normal voltage mode to the low voltage mode, operating the memory cells at a second voltage across each of the memory cells, wherein the second voltage is lower than the first voltage. The method further includes performing an access on a subset of the memory cells while maintaining the second voltage across the memory cells.
摘要翻译：一种存储器，包括存储器单元，其中存储器被配置为在正常电压模式和低电压模式下操作。该方法包括在正常电压模式期间，以每个存储器单元的第一电压操作存储器单元。该方法还包括在从正常电压模式转换到低电压模式时，在每个存储单元上以第二电压操作存储单元，其中第二电压低于第一电压。该方法还包括在保持存储器单元两端的第二电压的同时对存储器单元的子集执行访问。

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