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    • 3. 发明申请
    • ADVANCED TELECOMMUNICATIONS ROUTER AND CROSSBAR SWITCH CONTROLLER
    • 高级电信路由器和交叉开关控制器
    • US20110013643A1
    • 2011-01-20
    • US12890551
    • 2010-09-24
    • Brian Hang Wai YangKai-Yeung (Sunny) SiuMizanur M. RahmanWei-Han LienGaurav Singh
    • Brian Hang Wai YangKai-Yeung (Sunny) SiuMizanur M. RahmanWei-Han LienGaurav Singh
    • H04L12/56
    • H04L49/25H04L49/101H04L49/3027H04L49/3045
    • The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. The invention also includes a matrix circuit coupled to the input terminal and configured to represent the set of service request signals in the form of a matrix, wherein each service request signal is described by a row position M and a column position N. The invention further includes an output terminal configured to receive a portion of the set of packets during an epoch, an arbiter circuit configured to iteratively scan the matrix during the epoch and issue the set of grant signals to the virtual output queues to determine which service requests are granted, and an arbiter controller configured to initiate the arbiter circuit with an array of non-conflicting matrix elements. Whereby, the arbiter circuit scans the matrix during a first epoch, issues the set of grant signals, allows the set of granted service requests to substantially complete, and if necessary, scans the matrix during subsequent epochs. The invention also relates to a crossbar switch controller including an arbitration pre-processor coupled to the input terminal and the matrix circuit, and configured to represent the set of service request signals in the form of a mapping matrix, and further configured to transform a first mapping position of the service request signal to a second mapping position based, in part, on a mapping algorithm. The invention also includes an arbitration post-processor coupled to the output terminal and the matrix circuit, and further configured to transform the second mapping position of the service request signal back to the first mapping position.
    • 本发明涉及一种交叉开关控制器,其包括输入端子,该输入端子被配置为从包括一组分组的一组虚拟输出队列接收一组服务请求信号。 本发明还包括耦合到输入端并被配置为以矩阵的形式表示服务请求信号集合的矩阵电路,其中每个服务请求信号由行位置M和列位置N描述。本发明进一步 包括被配置为在历元期间接收所述一组分组的一部分的输出终端,所述仲裁器电路被配置为在所述时期期间迭代地扫描所述矩阵,并向所述虚拟输出队列发出所述一组授权信号以确定哪些服务请求被授权, 以及仲裁器控制器,被配置为使用非冲突矩阵元素的阵列启动仲裁器电路。 由此,仲裁器电路在第一纪元期间扫描矩阵,发出授权信号集合,允许一组授权的服务请求基本上完成,并且如果需要,在随后的时期期间扫描矩阵。 本发明还涉及一种交叉开关控制器,其包括耦合到输入端和矩阵电路的仲裁预处理器,并且被配置为以映射矩阵的形式表示该组服务请求信号,并且还被配置为将第一 部分地基于映射算法将服务请求信号的映射位置映射到第二映射位置。 本发明还包括耦合到输出端和矩阵电路的仲裁后处理器,还被配置为将服务请求信号的第二映射位置转换回第一映射位置。
    • 4. 发明申请
    • AGE MATRIX FOR QUEUE DISPATCH ORDER
    • 年龄排序的年龄矩阵
    • US20080320478A1
    • 2008-12-25
    • US11830727
    • 2007-07-30
    • Gaurav SinghSrivatsan SrinivasanLintsung Wong
    • Gaurav SinghSrivatsan SrinivasanLintsung Wong
    • G06F9/46
    • G06F9/3814G06F9/3838
    • An apparatus for queue allocation. An embodiment of the apparatus includes a dispatch order data structure, a bit vector, and a queue controller. The dispatch order data structure corresponds to a queue. The dispatch order data structure stores a plurality of dispatch indicators associated with a plurality of pairs of entries of the queue to indicate a write order of the entries in the queue. The bit vector stores a plurality of mask values corresponding to the dispatch indicators of the dispatch order data structure. The queue controller interfaces with the queue and the dispatch order data structure. The queue controller excludes at least some of the entries from a queue operation based on the mask values of the bit vector.
    • 一种用于队列分配的装置。 该装置的实施例包括调度顺序数据结构,位向量和队列控制器。 调度订单数据结构对应于一个队列。 调度订单数据结构存储与队列的多对条目相关联的多个调度指示符,以指示队列中条目的写入顺序。 位向量存储对应于调度顺序数据结构的调度指示符的多个掩码值。 队列控制器与队列和调度订单数据结构接口。 队列控制器基于位向量的掩码值从队列操作中排除至少一些条目。