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1. 发明授权

US08754546B2 Bulk power assembly 有权
标题翻译：散装电源组件
公开(公告)号：US08754546B2
公开(公告)日：2014-06-17
申请号：US12425275
申请日：2009-04-16
申请人： Ravi Kumar Arimilli , Edward Joseph Seminaro , Kevin Robert Covi , Steven John Ahladas
发明人： Ravi Kumar Arimilli , Edward Joseph Seminaro , Kevin Robert Covi , Steven John Ahladas
IPC分类号： H02J1/00
CPC分类号： H05K7/1492 , H02J1/102 , Y10T307/344 , Y10T307/352 , Y10T307/391 , Y10T307/406 , Y10T307/62 , Y10T307/707
摘要： A bulk power assembly includes a bulk power distribution (BPD) subassembly and a bulk power controller and hub (BPCH) subassembly coupled to the BPD subassembly. The BPD assembly is configured to provide bulk DC power from both AC input power and DC input power. The BPD subassembly is configured to distribute the DC bulk power. The BPCH subassembly is configured to monitor and control the BPD assembly.
摘要翻译：散装电源组件包括耦合到BPD子组件的大容量配电（BPD）子组件和大容量功率控制器和集线器（BPCH）子组件。 BPD组件配置为从交流输入电源和直流输入电源提供批量直流电源。 BPD子组件配置为分配DC大容量电源。 BPCH子组件被配置为监视和控制BPD组件。

2. 发明申请

US20100264733A1 BULK POWER ASSEMBLY 有权
标题翻译：大功率组件
公开(公告)号：US20100264733A1
公开(公告)日：2010-10-21
申请号：US12425275
申请日：2009-04-16
申请人： Ravi Kumar Arimilli , Edward Joseph Seminaro , Kevin Robert Covi , Steven John Ahladas
发明人： Ravi Kumar Arimilli , Edward Joseph Seminaro , Kevin Robert Covi , Steven John Ahladas
IPC分类号： H02J1/00 , H02B1/56 , H02B1/26
CPC分类号： H05K7/1492 , H02J1/102 , Y10T307/344 , Y10T307/352 , Y10T307/391 , Y10T307/406 , Y10T307/62 , Y10T307/707
摘要： A bulk power assembly includes a bulk power distribution (BPD) subassembly and a bulk power controller and hub (BPCH) subassembly coupled to the BPD subassembly. The BPD assembly is configured to provide bulk DC power from both AC input power and DC input power. The BPD subassembly is configured to distribute the DC bulk power. The BPCH subassembly is configured to monitor and control the BPD assembly.
摘要翻译：散装电源组件包括耦合到BPD子组件的大容量配电（BPD）子组件和大容量功率控制器和集线器（BPCH）子组件。 BPD组件配置为从交流输入电源和直流输入电源提供批量直流电源。 BPD子组件配置为分配DC大容量电源。 BPCH子组件被配置为监视和控制BPD组件。

3. 发明授权

US08018095B2 Power conversion, control, and distribution system 有权
标题翻译：电力转换，控制和配电系统
公开(公告)号：US08018095B2
公开(公告)日：2011-09-13
申请号：US12425267
申请日：2009-04-16
申请人： Ravi Kumar Arimilli , Edward Joseph Seminaro , Kevin Robert Covi , Gerald J. Fahr , Daniel James Barus
发明人： Ravi Kumar Arimilli , Edward Joseph Seminaro , Kevin Robert Covi , Gerald J. Fahr , Daniel James Barus
IPC分类号： H02J3/38
CPC分类号： H02J1/102 , Y10T307/352 , Y10T307/707
摘要： A power conversion, control, and distribution system includes multiple bulk power regulator (BPR) subassemblies, a bulk power distribution (BPD) subassembly, and a bulk power controller and hub (BPCH) subassembly. The BPR subassemblies are each configured to provide regulated DC power from both AC input power and DC input power. The BPD subassembly is configured to distribute the regulated DC power. The BPCH subassembly is coupled to the multiple BPR subassemblies and the BPD subassembly. The BPCH subassembly is configured to monitor and control the BPR assemblies and the BPD assembly.
摘要翻译：电力转换，控制和分配系统包括多个大功率调节器（BPR）子组件，大容量配电（BPD）子组件和大容量功率控制器和集线器（BPCH）子组件。 BPR子组件各自配置为从交流输入功率和直流输入功率提供稳压的直流电源。 BPD子组件被配置为分配调节的直流电力。 BPCH子组件耦合到多个BPR子组件和BPD子组件。 BPCH子组件被配置为监视和控制BPR组件和BPD组件。

4. 发明申请

US20100264731A1 POWER CONVERSION, CONTROL, AND DISTRIBUTION SYSTEM 有权
标题翻译：电力转换，控制和分配系统
公开(公告)号：US20100264731A1
公开(公告)日：2010-10-21
申请号：US12425267
申请日：2009-04-16
申请人： Ravi Kumar Arimilli , Edward Joseph Seminaro , Kevin Covi , Gerald J. Fahr , Daniel James Barus
发明人： Ravi Kumar Arimilli , Edward Joseph Seminaro , Kevin Covi , Gerald J. Fahr , Daniel James Barus
IPC分类号： H02J4/00
CPC分类号： H02J1/102 , Y10T307/352 , Y10T307/707
摘要： A power conversion, control, and distribution system includes multiple bulk power regulator (BPR) subassemblies, a bulk power distribution (BPD) subassembly, and a bulk power controller and hub (BPCH) subassembly. The BPR subassemblies are each configured to provide regulated DC power from both AC input power and DC input power. The BPD subassembly is configured to distribute the regulated DC power. The BPCH subassembly is coupled to the multiple BPR subassemblies and the BPD subassembly. The BPCH subassembly is configured to monitor and control the BPR assemblies and the BPD assembly.
摘要翻译：电力转换，控制和分配系统包括多个大功率调节器（BPR）子组件，大容量配电（BPD）子组件和大容量功率控制器和集线器（BPCH）子组件。 BPR子组件各自配置为从交流输入功率和直流输入功率提供稳压的直流电源。 BPD子组件被配置为分配调节的直流电力。 BPCH子组件耦合到多个BPR子组件和BPD子组件。 BPCH子组件被配置为监视和控制BPR组件和BPD组件。

5. 发明授权

US08122132B2 Techniques for dynamically assigning jobs to processors in a cluster based on broadcast information 有权
标题翻译：基于广播信息将作业动态地分配给集群中的处理器的技术
公开(公告)号：US08122132B2
公开(公告)日：2012-02-21
申请号：US12336312
申请日：2008-12-16
申请人： Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , Claude Basso , Jean L. Calvignac
发明人： Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , Claude Basso , Jean L. Calvignac
IPC分类号： G06F13/00
CPC分类号： G06F9/5088
摘要： A technique for operating a high performance computing cluster (HPC) having multiple nodes (each of which include multiple processors) includes periodically broadcasting information, related to processor utilization and network utilization at each of the multiple nodes, from each of the multiple nodes to remaining ones of the multiple nodes. Respective local job tables maintained in each of the multiple nodes are updated based on the broadcast information. One or more threads are then moved from one or more of the multiple processors to a different one of the multiple processors (based on the broadcast information in the respective local job tables).
摘要翻译：用于操作具有多个节点（每个包括多个处理器）的高性能计算群集（HPC）的技术包括：从多个节点中的每个节点到多个节点周期性地广播与多个节点中的每个节点处的处理器利用和网络利用相关的信息多个节点中的一个。基于广播信息来更新维护在多个节点中的每个节点的相应的本地作业表。然后，一个或多个线程从多个处理器中的一个或多个移动到多个处理器中的不同处理器（基于相应的本地作业表中的广播信息）。

6. 发明申请

US20100268880A1 Dynamic Runtime Modification of Array Layout for Offset 有权
标题翻译：用于偏移的阵列布局的动态运行时修改
公开(公告)号：US20100268880A1
公开(公告)日：2010-10-21
申请号：US12424348
申请日：2009-04-15
申请人： Ravi Kumar Arimilli , Donald W. Plass , William John Starke
发明人： Ravi Kumar Arimilli , Donald W. Plass , William John Starke
IPC分类号： G06F12/08 , G06F1/12
CPC分类号： G06F12/0886 , G06F9/30047 , G06F9/345
摘要： Disclosed are a method, a system and a computer program product for operating a cache system. The cache system can include multiple cache lines, and a first cache line of the multiple of cache lines can include multiple cache cells, and a bus coupled to the multiple cache cells. In one or more embodiments, the bus can include a switch that is operable to receive a first control signal and to split the bus into first and second portions or aggregate the bus into a whole based on the first control signal. When the bus is split, a first cache cell and a second cache cell of the multiple cache cells are coupled to respective first and second portions of the bus. Data from the first and second cache cells can be selected through respective portions of the bus and outputted through a port of the cache system.
摘要翻译：公开了一种用于操作缓存系统的方法，系统和计算机程序产品。高速缓存系统可以包括多个高速缓存行，并且多条高速缓存行的第一高速缓存行可以包括多个高速缓存单元，以及耦合到多个高速缓存单元的总线。在一个或多个实施例中，总线可以包括可操作以接收第一控制信号并且将总线分为第一和第二部分或基于第一控制信号将总线聚合成整体的开关。当总线被分离时，多个高速缓存单元的第一高速缓存单元和第二高速缓存单元耦合到总线的相应的第一和第二部分。可以通过总线的各个部分选择来自第一和第二高速缓存单元的数据，并通过高速缓存系统的端口输出。

7. 发明授权

US07818364B2 Method and data processing system for microprocessor communication in a cluster-based multi-processor system 失效
标题翻译：基于群集的多处理器系统中微处理器通信的方法和数据处理系统
公开(公告)号：US07818364B2
公开(公告)日：2010-10-19
申请号：US11952479
申请日：2007-12-07
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F15/76 , G06F15/163
CPC分类号： H04L69/16 , G06F15/17 , H04L12/42 , H04L67/1002 , H04L69/161 , H04W28/14
摘要： A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：包含在多处理器集群系统内的处理器通信寄存器（PCR）提供增强的处理器通信。 PCR存储在流水线或并行多处理中有用的信息。每个处理器集群具有存储到PCR中的扇区的独占权限，并且具有连续访问以读取其内容。每个处理器集群在PCR中更新其独占部分，立即允许集群网络内的所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存行，从而压倒互连和内存系统具有无限的加载流，存储和无效命令。

8. 发明申请

US20100153541A1 TECHNIQUES FOR DYNAMICALLY ASSIGNING JOBS TO PROCESSORS IN A CLUSTER BASED ON PROCESSOR WORKLOAD 有权
标题翻译：基于处理器工作负载的集群中的处理器动态组织工作的技术
公开(公告)号：US20100153541A1
公开(公告)日：2010-06-17
申请号：US12336256
申请日：2008-12-16
申请人： Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , Claude Basso , Jean L. Calvignac
发明人： Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , Claude Basso , Jean L. Calvignac
IPC分类号： G06F15/173
CPC分类号： G06F9/5088
摘要： A technique for operating a high performance computing (HPC) cluster includes monitoring workloads of multiple processors included in the HPC cluster. The HPC cluster includes multiple nodes that each include two or more of the multiple processors. One or more threads assigned to one or more of the multiple processors are moved to a different one of the multiple processors based on the workloads of the multiple processors.
摘要翻译：用于操作高性能计算（HPC）集群的技术包括监视包含在HPC集群中的多个处理器的工作负载。 HPC集群包括多个节点，每个节点包含多个处理器中的两个或多个。基于多个处理器的工作负载，分配给多个处理器中的一个或多个的一个或多个线程被移动到多个处理器中的不同处理器。

9. 发明授权

US07617378B2 Multiprocessor system with retry-less TLBI protocol 失效
标题翻译：具有重试TLBI协议的多处理器系统
公开(公告)号：US07617378B2
公开(公告)日：2009-11-10
申请号：US10425402
申请日：2003-04-28
申请人： Ravi Kumar Arimilli , Guy Lynn Guthrie , Kirk Samuel Livingston
发明人： Ravi Kumar Arimilli , Guy Lynn Guthrie , Kirk Samuel Livingston
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/682 , G06F2212/683
摘要： A symmetric multiprocessor data processing system (SMP) that implements a TLBI protocol, which enables multiple TLBI operations from multiple processors to complete without causing delay. Each processor includes a TLBI register associated with the TLB and TLBI logic. The TLBI register includes a sequence of bits utilized to track the completion of a TLBI issued by the processor at the other processors. Each bit corresponds to a particular processor across the system and the particular processor is able to directly set the bit in the register of a master processor once the particular processor completes a TLBI operation initiated from the master processor. The master processor is able to track completion of the TLBI operation by checking the values of each bit within its TLBI register, without requiring multi-issuance of an address-only barrier operation on the system bus.
摘要翻译：实现TLBI协议的对称多处理器数据处理系统（SMP），使多个处理器的多个TLBI操作能够完成而不会造成延迟。每个处理器包括与TLB和TLBI逻辑相关联的TLBI寄存器。 TLBI寄存器包括用于跟踪由处理器在其他处理器发出的TLBI的完成的位的序列。每个位对应于跨系统的特定处理器，并且特定处理器能够在特定处理器完成从主处理器发起的TLBI操作之后直接设置主处理器的寄存器中的位。主处理器能够通过检查其TLBI寄存器中每个位的值来跟踪完成TLBI操作，而不需要在系统总线上多次发出仅地址唯一的屏蔽操作。

10. 发明授权

US07586936B2 Host Ethernet adapter for networking offload in server environment 失效
标题翻译：主机以太网适配器，用于在服务器环境中进行网络卸载
公开(公告)号：US07586936B2
公开(公告)日：2009-09-08
申请号：US11097608
申请日：2005-04-01
申请人： Ravi Kumar Arimilli , Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Ronald Edward Fuhs , Satya Prakash Sharma , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg
发明人： Ravi Kumar Arimilli , Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Ronald Edward Fuhs , Satya Prakash Sharma , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg
IPC分类号： H04L12/66
CPC分类号： H04L12/413 , H04L12/40032 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/324
摘要： An Ethernet adapter is disclosed. The Ethernet adapter comprises a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor. The plurality of layers include a demultiplexing mechanism to allow for partitioning of the processor. A Host Ethernet Adapter (HEA) is an integrated Ethernet adapter providing a new approach to Ethernet and TCP acceleration. A set of TCP/IP acceleration features have been introduced in a toolkit approach: Servers TCP/IP stacks use these accelerators when and as required. The interface between the server and the network interface controller has been streamlined by bypassing the PCI bus. The HEA supports network virtualization. The HEA can be shared by multiple OSs providing the essential isolation and protection without affecting its performance.
摘要翻译：公开了一种以太网适配器。以太网适配器包括多个层，用于允许适配器从处理器接收和发送分组。多个层包括多路分解机制以允许处理器的划分。主机以太网适配器（HEA）是集成的以太网适配器，为以太网和TCP加速提供了新的方法。一组TCP / IP加速功能已经在工具包方法中引入：服务器TCP / IP堆栈在需要时使用这些加速器。服务器和网络接口控制器之间的接口通过绕过PCI总线进行了简化。 HEA支持网络虚拟化。 HEA可以由多个操作系统共享，提供基本的隔离和保护，而不会影响其性能。

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