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1. 发明授权

US07493417B2 Method and data processing system for microprocessor communication using a processor interconnect in a multi-processor system 失效
标题翻译：用于在多处理器系统中使用处理器互连的微处理器通信的方法和数据处理系统
公开(公告)号：US07493417B2
公开(公告)日：2009-02-17
申请号：US10318515
申请日：2002-12-12
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F15/16
CPC分类号： G06F15/167
摘要： Processor communication registers (PCRs) contained in each processor within a multiprocessor system and interconnected by a specialized bus provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs utilizing communication over the specialized bus, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：处理器通信寄存器（PCR）包含在多处理器系统中的每个处理器中并由专用总线互连提供增强的处理器通信。每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。每个处理器具有存储在每个PCR内的扇区的专有权利，并且具有连续访问以读取其自己的PCR的内容。每个处理器利用专用总线上的通信在所有PCR中更新其独占扇区，立即允许所有其他处理器查看PCR数据内的变化，并绕过高速缓存子系统。通过提供处理器通信以立即转移到所有处理器中而不会立即限制对信息的访问或迫使所有处理器连续地竞争相同的高速缓存行，从而将互连和存储系统压倒在一起，从而在多处理器系统中提高效率无限流的加载，存储和无效命令。

2. 发明授权

US07818364B2 Method and data processing system for microprocessor communication in a cluster-based multi-processor system 失效
标题翻译：基于群集的多处理器系统中微处理器通信的方法和数据处理系统
公开(公告)号：US07818364B2
公开(公告)日：2010-10-19
申请号：US11952479
申请日：2007-12-07
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F15/76 , G06F15/163
CPC分类号： H04L69/16 , G06F15/17 , H04L12/42 , H04L67/1002 , H04L69/161 , H04W28/14
摘要： A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：包含在多处理器集群系统内的处理器通信寄存器（PCR）提供增强的处理器通信。 PCR存储在流水线或并行多处理中有用的信息。每个处理器集群具有存储到PCR中的扇区的独占权限，并且具有连续访问以读取其内容。每个处理器集群在PCR中更新其独占部分，立即允许集群网络内的所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存行，从而压倒互连和内存系统具有无限的加载流，存储和无效命令。

3. 发明授权

US07356568B2 Method, processing unit and data processing system for microprocessor communication in a multi-processor system 失效
标题翻译：用于多处理器系统中微处理器通信的方法，处理单元和数据处理系统
公开(公告)号：US07356568B2
公开(公告)日：2008-04-08
申请号：US10318514
申请日：2002-12-12
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F13/00
CPC分类号： G06F9/30101
摘要： A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：包含在多处理器系统内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。每个处理器具有存储在每个PCR内的扇区的专有权利，并且具有连续访问以读取其自己的PCR的内容。每个处理器在所有PCR中更新其独占扇区，立即允许所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。通过提供处理器通信以立即转移到所有处理器中而不会立即限制对信息的访问或迫使所有处理器连续地竞争相同的高速缓存行，从而将互连和存储系统压倒在一起，从而在多处理器系统中提高效率无限流的加载，存储和无效命令。

4. 发明授权

US07698373B2 Method, processing unit and data processing system for microprocessor communication in a multi-processor system 失效
标题翻译：用于多处理器系统中微处理器通信的方法，处理单元和数据处理系统
公开(公告)号：US07698373B2
公开(公告)日：2010-04-13
申请号：US11971959
申请日：2008-01-10
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F13/00
CPC分类号： G06F9/30101
摘要： A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：包含在多处理器系统内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。每个处理器具有存储在每个PCR内的扇区的专有权利，并且具有连续访问以读取其自己的PCR的内容。每个处理器在所有PCR中更新其独占扇区，立即允许所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。通过提供处理器通信以立即转移到所有处理器中而不会立即限制对信息的访问或迫使所有处理器连续地竞争相同的高速缓存行，从而将互连和存储系统压倒在一起，从而在多处理器系统中提高效率无限流的加载，存储和无效命令。

5. 发明授权

US07734877B2 Method and data processing system for processor-to-processor communication in a clustered multi-processor system 失效
标题翻译：用于集群多处理器系统中处理器到处理器通信的方法和数据处理系统
公开(公告)号：US07734877B2
公开(公告)日：2010-06-08
申请号：US11954686
申请日：2007-12-12
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F13/00
CPC分类号： G06F15/173 , H04W28/14
摘要： A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：包含在多处理器集群网络内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。每个处理器具有在群集网络内的每个PCR内存储到扇区的专有权限，并且具有连续访问以读取其自己的PCR的内容。每个处理器通过专用协议或专用无线网络在所有PCR内更新其独占部分，立即允许集群网络内的所有其他处理器在PCR数据中查看变化，并绕过缓存子系统。处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存线，从而压倒互连和内存系统具有无限的加载流，存储和无效命令。

6. 发明申请

US20080155231A1 METHOD AND DATA PROCESSING SYSTEM FOR PROCESSOR-TO-PROCESSOR COMMUNICATION IN A CLUSTERED MULTI-PROCESSOR SYSTEM 失效
标题翻译：集成多处理器系统中处理器到处理器通信的方法和数据处理系统
公开(公告)号：US20080155231A1
公开(公告)日：2008-06-26
申请号：US11954686
申请日：2007-12-12
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F15/76 , G06F9/00
CPC分类号： G06F15/173 , H04W28/14
摘要： A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：包含在多处理器集群网络内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。每个处理器具有在群集网络内的每个PCR内存储到扇区的专有权限，并且具有连续访问以读取其自己的PCR的内容。每个处理器通过专用协议或专用无线网络在所有PCR内更新其独占部分，立即允许集群网络内的所有其他处理器在PCR数据中查看变化，并绕过缓存子系统。处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存线，从而压倒互连和内存系统具有无限的加载流，存储和无效命令。

7. 发明授权

US07360067B2 Method and data processing system for microprocessor communication in a cluster-based multi-processor wireless network 有权
标题翻译：基于群集的多处理器无线网络中微处理器通信的方法和数据处理系统
公开(公告)号：US07360067B2
公开(公告)日：2008-04-15
申请号：US10318513
申请日：2002-12-12
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F15/173
CPC分类号： G06F15/173 , H04W28/14
摘要： A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：包含在多处理器集群网络内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。每个处理器具有在群集网络内的每个PCR内存储到扇区的专有权限，并且具有连续访问以读取其自己的PCR的内容。每个处理器通过专用协议或专用无线网络在所有PCR内更新其独占部分，立即允许集群网络内的所有其他处理器在PCR数据中查看变化，并绕过缓存子系统。处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存线，从而压倒互连和内存系统具有无限的加载流，存储和无效命令。

8. 发明授权

US07359932B2 Method and data processing system for microprocessor communication in a cluster-based multi-processor system 失效
标题翻译：基于群集的多处理器系统中微处理器通信的方法和数据处理系统
公开(公告)号：US07359932B2
公开(公告)日：2008-04-15
申请号：US10318516
申请日：2002-12-12
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F15/76 , G06F15/163
CPC分类号： H04L69/16 , G06F15/17 , H04L12/42 , H04L67/1002 , H04L69/161 , H04W28/14
摘要： A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：包含在多处理器集群系统内的处理器通信寄存器（PCR）提供增强的处理器通信。 PCR存储在流水线或并行多处理中有用的信息。每个处理器集群具有存储到PCR中的扇区的独占权限，并且具有连续访问以读取其内容。每个处理器集群在PCR中更新其独占部分，立即允许集群网络内的所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存线，从而压倒互连和内存系统具有无限的加载流，存储和无效命令。

9. 发明授权

US06920521B2 Method and system of managing virtualized physical memory in a data processing system 失效
标题翻译：在数据处理系统中管理虚拟物理存储器的方法和系统
公开(公告)号：US06920521B2
公开(公告)日：2005-07-19
申请号：US10268741
申请日：2002-10-10
申请人： Ravi Kumar Arimilli , John Steven Dodson , Sanjeev Ghai , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , John Steven Dodson , Sanjeev Ghai , Kenneth Lee Wright
IPC分类号： G06F12/00 , G06F12/02 , G06F12/06 , G06F12/08
CPC分类号： G06F12/0292 , G06F12/0646
摘要： A move engine and operating system transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. The operating system stores FROM and TO real addresses in unique fields in memory that are used to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the FROM and TO real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory module. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space. During the process of moving the memory contents, the operating system stalls. Write memory requests addressed to the real address space currently associated with the sourcing memory module indicated by either the FROM or TO real address space. As will be appreciated, a memory module can be inserted, removed or replaced in physical memory without the operating system having to stop all memory operations in the memory to accomplish the physical memory change.
摘要翻译：移动引擎和操作系统透明地重新配置物理内存以实现内存模块的加法，减法或更换。操作系统将FROM和TO存储在存储器中的唯一字段中存储，用于虚拟化正在重新配置的存储器模块的物理地址，并通过使用硬件功能而不是软件来实时提供重新配置。使用FROM和TO实地址选择源和目标，移动引擎将要删除或重新配置的内存模块的内容复制到剩余或插入的内存模块中。然后，将与重新配置的存储器模块相关联的真实地址重新分配给接收复制内容的存储器模块，从而由操作系统利用的可寻址实地址空间创建虚拟物理映射到虚拟物理地址空间。在移动存储器内容的过程中，操作系统停顿。将存储器请求写入到由FROM或TO实地址空间指示的当前与源存储器模块相关联的实际地址空间。如将理解的，可以在物理存储器中插入，移除或替换存储器模块，而不需要操作系统停止存储器中的所有存储器操作来完成物理存储器改变。

10. 发明授权

US07017024B2 Data processing system having no system memory 失效
标题翻译：数据处理系统没有系统内存
公开(公告)号：US07017024B2
公开(公告)日：2006-03-21
申请号：US10319023
申请日：2002-12-12
申请人： Ravi Kumar Arimilli , John Steven Dodson , Sanjeev Ghai , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , John Steven Dodson , Sanjeev Ghai , Kenneth Lee Wright
IPC分类号： G06F12/10
CPC分类号： G06F12/0802 , G06F12/08 , Y02D10/13
摘要： A data processing system having no system memory is disclosed. The data processing system includes multiple processing units. The processing units have volatile cache memories operating in a virtual address space that is greater than a real address space. The processing units and the respective volatile memories are coupled to a storage controller operating in a physical address space that is equal to the virtual address space. The processing units and the storage controller are coupled to a hard disk via an interconnect. The storage controller allows the mapping of a virtual address from one of the volatile cache memories to a physical disk address directed to a storage location within the hard disk without transitioning through a real address.
摘要翻译：公开了一种没有系统存储器的数据处理系统。数据处理系统包括多个处理单元。处理单元具有在大于真实地址空间的虚拟地址空间中操作的易失性高速缓存存储器。处理单元和相应的易失性存储器耦合到在等于虚拟地址空间的物理地址空间中操作的存储控制器。处理单元和存储控制器通过互连耦合到硬盘。存储控制器允许将虚拟地址从一个易失性高速缓存存储器映射到指向硬盘内的存储位置的物理磁盘地址，而不转换真实地址。

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