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1. 发明授权

US07682842B2 Method of adaptively selecting chips for reducing in-line testing in a semiconductor manufacturing line 失效
标题翻译：自适应选择芯片以减少半导体生产线中的在线测试的方法
公开(公告)号：US07682842B2
公开(公告)日：2010-03-23
申请号：US12129712
申请日：2008-05-30
申请人： Rao H. Desineni , Xu Ouyang , Hargurpreet Singh , Yunsheng Song , Stephen Wu
发明人： Rao H. Desineni , Xu Ouyang , Hargurpreet Singh , Yunsheng Song , Stephen Wu
IPC分类号： H01L21/00
CPC分类号： G01R31/2894
摘要： A method for identifying potentially defective integrated circuit chips and excluding them from future testing as wafers move through a manufacturing line The method includes data-collecting steps, tagging the chips on wafers identified as potentially bad chips based on information collected as the wafer moves down the fabrication line, evaluating test cost savings by eliminating any further tests on the tagged chips preferably using a test cost database. Considering all the future tests to be preformed, the tagged chips are skipped if it is determined that the test cost saving is significant. Tagging bad chips is based on various criteria and models which are dynamically adjusted by performing the wafer final test on samples of the tagged chips and feeding-back the final test results. The dynamic adaptive adjustment method preferably includes a feedback loop or iterative process to evaluate financial tradeoffs when assessing the profit of salvaging chips against the additional test costs.
摘要翻译：一种用于识别潜在有缺陷的集成电路芯片的方法，并将其从将来的测试中排除，因为晶片移动通过生产线。该方法包括数据收集步骤，基于当晶片向下移动时收集的信息将标记为潜在的坏芯片的晶片上的芯片标记通过消除对标记芯片的任何进一步测试，优选使用测试成本数据库来评估测试成本节省。考虑到将要执行的所有将来的测试，如果确定测试成本节省是重要的，则标记的芯片被跳过。标记坏芯片是基于各种标准和模型，通过对标记芯片的样品进行晶圆最终测试并反馈最终测试结果来动态调整。动态自适应调整方法优选地包括反馈循环或迭代过程，以在评估补救筹码的利润与额外的测试成本时评估金融权衡。

2. 发明授权

US08369976B2 Method for compensating for tool processing variation in the routing of wafers/lots 失效
标题翻译：补偿晶圆/批次布线中刀具加工变化的方法
公开(公告)号：US08369976B2
公开(公告)日：2013-02-05
申请号：US12144093
申请日：2008-06-23
申请人： Keith Kwong Hon Wong , Xu Ouyang , Yunsheng Song
发明人： Keith Kwong Hon Wong , Xu Ouyang , Yunsheng Song
IPC分类号： G06F19/00
CPC分类号： H01L22/20 , H01L22/12
摘要： A method for increasing overall yield in semiconductor manufacturing including routing wafers or wafer lots from tool to tool in a manner which at least partially neutralizes or compensates for processing variations. A system for increasing overall yield in semiconductor manufacturing includes a module for recording processing data from plural first and second types of tools and a module for routing wafers or wafer lots from tools of the first type of tools to tools of the second type of tools so as to at least partially neutralizes or compensate for processing variation.
摘要翻译：一种用于提高半导体制造中的总产量的方法，包括以至少部分中和或补偿处理变化的方式从工具到工具路由晶圆或晶片批次。用于提高半导体制造中的整体产量的系统包括用于记录来自多个第一和第二类型工具的处理数据的模块和用于将晶片或晶片批次从第一类型工具的工具转移到第二类型工具的工具的模块，至少部分地中和或补偿处理变化。

3. 发明申请

US20130169308A1 LCR TEST CIRCUIT STRUCTURE FOR DETECTING METAL GATE DEFECT CONDITIONS 有权
标题翻译：用于检测金属门缺陷条件的LCR测试电路结构
公开(公告)号：US20130169308A1
公开(公告)日：2013-07-04
申请号：US13343080
申请日：2012-01-04
申请人： Xu Ouyang , Yunsheng Song , Tso-Hui Ting , Yongchun Xin
发明人： Xu Ouyang , Yunsheng Song , Tso-Hui Ting , Yongchun Xin
IPC分类号： G01R31/26
CPC分类号： H01L22/34 , G01R31/2858 , H01L2924/0002 , H01L2924/00
摘要： A test structure for an integrated circuit device includes a series inductor, capacitor, resistor (LCR) circuit having one or more inductor elements, with each inductor element having at least one unit comprising a first segment formed in a first metal layer, a second segment connecting the first metal layer to a semiconductor substrate beneath the first metal layer, and a third segment formed in the semiconductor substrate; and a capacitor element connected in series with each inductor element, the capacitor element defined by a transistor gate structure including a gate electrode as a first electrode, a gate dielectric layer, and the semiconductor substrate as a second electrode.
摘要翻译：集成电路器件的测试结构包括具有一个或多个电感器元件的串联电感器，电容器，电阻器（LCR）电路，每个电感器元件具有至少一个单元，该单元包括形成在第一金属层中的第一段，第二段将所述第一金属层连接到所述第一金属层下方的半导体基板，以及形成在所述半导体基板中的第三部分; 以及与每个电感器元件串联连接的电容器元件，所述电容器元件由包括作为第一电极的栅电极，栅介质层和作为第二电极的半导体衬底的晶体管栅极结构限定。

4. 发明授权

US08108803B2 Geometry based electrical hotspot detection in integrated circuit layouts 有权
标题翻译：集成电路布局中基于几何的电热点检测
公开(公告)号：US08108803B2
公开(公告)日：2012-01-31
申请号：US12603594
申请日：2009-10-22
申请人： Fook-Luen Heng , Xu Ouyang , Yunsheng Song , Yun-Yu Wang
发明人： Fook-Luen Heng , Xu Ouyang , Yunsheng Song , Yun-Yu Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/16
摘要： A method of failure detection of an integrated circuit (IC) layout includes determining a critical path distance between a first geometric feature of the IC layout and a second geometric feature of the IC layout; and comparing the determined critical path distance to a defined minimum critical path distance between the first and second geometric features, wherein the defined minimum critical path distance corresponds to a desired electrical property of the IC layout, independent of any geometric-based ground rule minimum distance for the IC layout; identifying any determined critical path distances that are less than the defined minimum critical path distance as a design violation; and modifying the IC layout by eliminating the identified design violations.
摘要翻译：集成电路（IC）布局的故障检测方法包括确定IC布局的第一几何特征与IC布局的第二几何特征之间的关键路径距离; 以及将所确定的关键路径距离与所述第一和第二几何特征之间的限定的最小关键路径距离进行比较，其中所述限定的最小关键路径距离对应于所述IC布局的所需电气特性，独立于任何基于几何的基准规则最小距离用于IC布局; 识别小于定义的最小关键路径距离的任何确定的关键路径距离作为设计违规; 并通过消除所识别的设计违规来修改IC布局。

5. 发明授权

US07962234B2 Multidimensional process window optimization in semiconductor manufacturing 有权
标题翻译：半导体制造中的多维过程窗口优化
公开(公告)号：US07962234B2
公开(公告)日：2011-06-14
申请号：US12135522
申请日：2008-06-09
申请人： Yunsheng Song , Xu Ouyang , James P. Rice
发明人： Yunsheng Song , Xu Ouyang , James P. Rice
IPC分类号： G06F19/00
CPC分类号： H01L22/20 , H01L22/12
摘要： A method for optimizing multiple process windows in a semiconductor manufacturing process is disclosed. The method comprises performing dependent variable composition on a plurality of dependent variables. Metrology data is joined with the dependent variables, and then a partial least squares regression is performed on the joined data set to obtain a prediction equation, and a variable importance prediction for each process window in a process window set. A set of product limited yield are derived, and the process window, set is adjusted, and the yields recalculated, until an optimal process window set is derived.
摘要翻译：公开了一种在半导体制造工艺中优化多个工艺窗口的方法。该方法包括在多个因变量上执行因变量组合。计量学数据与因变量相连，然后对连接的数据集执行偏最小二乘回归，以获得预测方程，并对过程窗口集中的每个过程窗口进行可变重要度预测。导出一组产品有限产量，并调整过程窗口集合，并重新计算产量，直到导出最优过程窗口集合。

6. 发明申请

US20110099529A1 GEOMETRY BASED ELECTRICAL HOTSPOT DETECTION IN INTEGRATED CIRCUIT LAYOUTS 有权
标题翻译：集成电路中基于几何的电气检测
公开(公告)号：US20110099529A1
公开(公告)日：2011-04-28
申请号：US12603594
申请日：2009-10-22
申请人： Fook-Luen Heng , Xu Ouyang , Yunsheng Song , Yun-Yu Wang
发明人： Fook-Luen Heng , Xu Ouyang , Yunsheng Song , Yun-Yu Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/16
摘要： A method of failure detection of an integrated circuit (IC) layout includes determining a critical path distance between a first geometric feature of the IC layout and a second geometric feature of the IC layout; and comparing the determined critical path distance to a defined minimum critical path distance between the first and second geometric features, wherein the defined minimum critical path distance corresponds to a desired electrical property of the IC layout, independent of any geometric-based ground rule minimum distance for the IC layout; identifying any determined critical path distances that are less than the defined minimum critical path distance as a design violation; and modifying the IC layout by eliminating the identified design violations.
摘要翻译：集成电路（IC）布局的故障检测方法包括确定IC布局的第一几何特征与IC布局的第二几何特征之间的关键路径距离; 以及将所确定的关键路径距离与所述第一和第二几何特征之间的限定的最小关键路径距离进行比较，其中所述限定的最小关键路径距离对应于所述IC布局的所需电气特性，独立于任何基于几何的基准规则最小距离用于IC布局; 识别小于定义的最小关键路径距离的任何确定的关键路径距离作为设计违规; 并通过消除所识别的设计违规来修改IC布局。

7. 发明申请

US20100201376A1 DETECTING ASYMMETRICAL TRANSISTOR LEAKAGE DEFECTS 有权
标题翻译：检测不对称晶体管漏电缺陷
公开(公告)号：US20100201376A1
公开(公告)日：2010-08-12
申请号：US12699211
申请日：2010-02-03
申请人： Xu Ouyang , Yun-Yu Wang , Yunsheng Song
发明人： Xu Ouyang , Yun-Yu Wang , Yunsheng Song
IPC分类号： H01H31/12
CPC分类号： H01L27/1104 , G11C11/41 , G11C29/50 , G11C2029/5006 , H01L22/34 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method of detecting low-probability defects in large transistor arrays (such as large arrays of SRAM cells), where the defects manifesting themselves as asymmetrical leakage in a transistor (such as a pulldown nFET in an SRAM cell). These defects are detected by creating one or more test arrays, identical in all regards to the large transistor arrays up until the contact and metallization layers. The test array(s) is (are) disposed side-by-side with the “normal” array(s) on the same reticle so that process variations that affect the normal array will also affect the test array. The contact and metallization layers for the test array are adapted to connect groups (sub-blocks) of transistors together in parallel for leakage testing. The group size is chosen to ensure that the leakage current associated with a single defective transistor is significantly greater than the aggregate leakage current associated with all of non-defective transistors in the group. Leakage is measured by applying an appropriate off-state voltage (e.g., 0V) by a common connection to all of the gates of the transistors in the test array, then measuring the aggregate drain/source leakage current, both forward and reverse (e.g., first grounded source and positively biased drain, then grounded drain and positively biased source) comparing the difference between the two leakage current measurements. The sub-blocks (groups) may be tested one at a time using a sub-block selection decoder to select the sub-block being tested.
摘要翻译：检测大晶体管阵列（例如大型SRAM单元阵列）中的低概率缺陷的方法，其中缺陷在晶体管（例如SRAM单元中的下拉nFET）中表现为非对称泄漏。通过创建一个或多个测试阵列来检测这些缺陷，所有这些测试阵列在大量晶体管阵列上相同，直到接触和金属化层。测试阵列与同一分划板上的“正常”阵列并排设置，从而影响正常阵列的过程变化也会影响测试阵列。用于测试阵列的接触和金属化层适于将晶体管的组（子块）并联连接在一起用于泄漏测试。选择组尺寸以确保与单个缺陷晶体管相关联的漏电流明显大于与组中的所有无缺陷晶体管相关的总漏电流。通过与测试阵列中的晶体管的所有栅极的公共连接施加适当的截止状态电压（例如，0V）来测量泄漏，然后测量正向和反向的汇总漏极/漏极电流（例如，第一接地源和正偏置漏极，然后接地漏极和正偏置源）比较两个漏电流测量值之间的差异。可以使用子块选择解码器一次一个地测试子块（组），以选择被测试的子块。

8. 发明授权

US09780007B2 LCR test circuit structure for detecting metal gate defect conditions 有权
公开(公告)号：US09780007B2
公开(公告)日：2017-10-03
申请号：US13343080
申请日：2012-01-04
申请人： Xu Ouyang , Yunsheng Song , Tso-Hui Ting , Yongchun Xin
发明人： Xu Ouyang , Yunsheng Song , Tso-Hui Ting , Yongchun Xin
IPC分类号： G01R31/02 , G01R31/26 , H01L21/66 , G01R31/28
CPC分类号： H01L22/34 , G01R31/2858 , H01L2924/0002 , H01L2924/00
摘要： A test structure for an integrated circuit device includes a series inductor, capacitor, resistor (LCR) circuit having one or more inductor elements, with each inductor element having at least one unit comprising a first segment formed in a first metal layer, a second segment connecting the first metal layer to a semiconductor substrate beneath the first metal layer, and a third segment formed in the semiconductor substrate; and a capacitor element connected in series with each inductor element, the capacitor element defined by a transistor gate structure including a gate electrode as a first electrode, a gate dielectric layer, and the semiconductor substrate as a second electrode.

9. 发明授权

US08294485B2 Detecting asymmetrical transistor leakage defects 有权
标题翻译：检测不对称晶体管漏电缺陷
公开(公告)号：US08294485B2
公开(公告)日：2012-10-23
申请号：US12699211
申请日：2010-02-03
申请人： Xu Ouyang , Yun-Yu Wang , Yunsheng Song
发明人： Xu Ouyang , Yun-Yu Wang , Yunsheng Song
IPC分类号： G01R31/02 , G01R31/08
CPC分类号： H01L27/1104 , G11C11/41 , G11C29/50 , G11C2029/5006 , H01L22/34 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method of detecting low-probability defects in large transistor arrays (such as large arrays of SRAM cells), where the defects manifest themselves as asymmetrical leakage in a transistor (such as a pulldown nFET in an SRAM cell). These defects are detected by creating one or more test arrays, identical in all regards to the large transistor arrays up until the contact and metallization layers. Leakage is measured by applying an appropriate off-state voltage (e.g., 0V) by a common connection to all of the gates of the transistors in the test array, then measuring the aggregate drain/source leakage current, both forward and reverse (e.g., first grounded source and positively biased drain, then grounded drain and positively biased source) comparing the difference between the two leakage current measurements.
摘要翻译：检测大晶体管阵列（例如大量SRAM单元阵列）中的低概率缺陷的方法，其中缺陷在晶体管（例如，SRAM单元中的下拉nFET）中表现为非对称泄漏。通过创建一个或多个测试阵列来检测这些缺陷，所有这些测试阵列在大量晶体管阵列上相同，直到接触和金属化层。通过与测试阵列中的晶体管的所有栅极的公共连接施加适当的截止状态电压（例如，0V）来测量泄漏，然后测量正向和反向的汇总漏极/漏极电流（例如，第一接地源和正偏置漏极，然后接地漏极和正偏置源）比较两个漏电流测量值之间的差异。

10. 发明申请

US20120232686A1 WAFER ALIGNMENT SYSTEM WITH OPTICAL COHERENCE TOMOGRAPHY 失效
标题翻译：具有光学相干坐标的波形对准系统
公开(公告)号：US20120232686A1
公开(公告)日：2012-09-13
申请号：US13042494
申请日：2011-03-08
申请人： Yongchun Xin , Xu Ouyang , Yunsheng Song , Tso-Hui Ting
发明人： Yongchun Xin , Xu Ouyang , Yunsheng Song , Tso-Hui Ting
IPC分类号： G05D3/00 , G06F15/00 , G01B9/02
CPC分类号： H01L21/681 , G01B9/02091 , H01L23/544 , H01L24/75 , H01L24/81 , H01L24/94 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2224/75753 , H01L2224/8113 , H01L2224/81132 , H01L2224/81191 , H01L2224/94 , H01L2224/81
摘要： A system for performing alignment of two wafers is disclosed. The system comprises an optical coherence tomography system and a wafer alignment system. The wafer alignment system is configured and disposed to control the relative position of a first wafer and a second wafer. The optical coherence tomography system is configured and disposed to compute coordinate data for a plurality of alignment marks on the first wafer and second wafer, and send that coordinate data to the wafer alignment system
摘要翻译：公开了一种用于执行两个晶片对准的系统。该系统包括光学相干断层摄影系统和晶片对准系统。晶片对准系统被配置和设置以控制第一晶片和第二晶片的相对位置。光学相干断层摄影系统被配置和设置为计算第一晶片和第二晶片上的多个对准标记的坐标数据，并将该坐标数据发送到晶片对准系统

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