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1. 发明授权

US09151781B2 Yield enhancement for stacked chips through rotationally-connecting-interposer 有权
标题翻译：通过旋转连接插入器对堆叠芯片的产量提高
公开(公告)号：US09151781B2
公开(公告)日：2015-10-06
申请号：US13397781
申请日：2012-02-16
申请人： Oleg Gluschenkov , Muthukumarasamy Karthikeyan , Yunsheng Song , Tso-Hui Ting , Richard P. Volant , Ping-Chuan Wang
发明人： Oleg Gluschenkov , Muthukumarasamy Karthikeyan , Yunsheng Song , Tso-Hui Ting , Richard P. Volant , Ping-Chuan Wang
IPC分类号： G01R31/26 , H01L23/58 , G01R1/073 , H01L21/66 , H01L25/00
CPC分类号： G01R1/07378 , H01L22/14 , H01L22/20 , H01L25/50 , H01L2225/06596 , H01L2924/0002 , H01L2924/00
摘要： A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i−1)/N×2π. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield.
摘要翻译：一组第一衬底和第二衬底被制造成围绕每个衬底的中心轴线具有内置的N倍旋转对称，其中N是大于1的整数。提供一组N个不同的插入件，（i-1）/ N×2＆pgr的转角提供第一基板和第二基板之间的电连接。测试第一和第二衬底中的每个N个不同的插入件。一旦确定了提供最高堆叠芯片产量的旋转角度，则可以以提供最高堆叠芯片产量的方位角旋转来接合第一和第二基板。

2. 发明授权

US08759152B2 Configurable interposer 有权
标题翻译：可配置插值器
公开(公告)号：US08759152B2
公开(公告)日：2014-06-24
申请号：US13489596
申请日：2012-06-06
申请人： Oleg Gluschenkov , Yunsheng Song , Tso-Hui Ting , Ping-Chuan Wang
发明人： Oleg Gluschenkov , Yunsheng Song , Tso-Hui Ting , Ping-Chuan Wang
IPC分类号： H01L21/00
CPC分类号： H01L23/49827 , H01L21/486 , H01L22/20 , H01L23/13 , H01L23/481 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L2224/0401 , H01L2224/0603 , H01L2224/1403 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2225/06596 , H01L2924/014 , H01L2924/1301 , H01L2924/1305 , H01L2924/15311 , H05K1/0286 , H05K1/142 , H05K2201/2018 , H05K2203/1572 , Y10T29/49117 , H01L2924/00
摘要： A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.
摘要翻译：模块化插入器包括多个插入器单元，其被组合以提供两个半导体芯片之间的完整的电连接。多个插入单元中的至少一些可以被具有替代配置的其它插入单元替代，以便能够通过模块化插入器选择要连接的半导体芯片的不同功能部件。连接到位于相邻插入单元周围的导电金属焊盘和半导体芯片的上部或下部的结合结构可以在相邻插入单元之间提供电连接。可以通过在衬底中形成贯穿衬底通孔（TSV）来形成插入器单元，在衬底上形成图案化的导电结构，并将衬底切割成插入层。

3. 发明授权

US08369976B2 Method for compensating for tool processing variation in the routing of wafers/lots 失效
标题翻译：补偿晶圆/批次布线中刀具加工变化的方法
公开(公告)号：US08369976B2
公开(公告)日：2013-02-05
申请号：US12144093
申请日：2008-06-23
申请人： Keith Kwong Hon Wong , Xu Ouyang , Yunsheng Song
发明人： Keith Kwong Hon Wong , Xu Ouyang , Yunsheng Song
IPC分类号： G06F19/00
CPC分类号： H01L22/20 , H01L22/12
摘要： A method for increasing overall yield in semiconductor manufacturing including routing wafers or wafer lots from tool to tool in a manner which at least partially neutralizes or compensates for processing variations. A system for increasing overall yield in semiconductor manufacturing includes a module for recording processing data from plural first and second types of tools and a module for routing wafers or wafer lots from tools of the first type of tools to tools of the second type of tools so as to at least partially neutralizes or compensate for processing variation.
摘要翻译：一种用于提高半导体制造中的总产量的方法，包括以至少部分中和或补偿处理变化的方式从工具到工具路由晶圆或晶片批次。用于提高半导体制造中的整体产量的系统包括用于记录来自多个第一和第二类型工具的处理数据的模块和用于将晶片或晶片批次从第一类型工具的工具转移到第二类型工具的工具的模块，至少部分地中和或补偿处理变化。

4. 发明申请

US20110077765A1 TOOL COMMONALITY AND STRATIFICATION ANALYSIS TO ENHANCE A PRODUCTION PROCESS 有权
标题翻译：工具共同和分析分析，以提高生产过程
公开(公告)号：US20110077765A1
公开(公告)日：2011-03-31
申请号：US12568083
申请日：2009-09-28
申请人： James Rice , Dustin K. Slisher , Yunsheng Song
发明人： James Rice , Dustin K. Slisher , Yunsheng Song
IPC分类号： G06F19/00
CPC分类号： G05B23/0294
摘要： A method of analyzing production steps includes inputting application data associated with a production process having a plurality of process steps into a memory with each of the plurality of process steps including a plurality of tools. The method also includes loading process data associated with one of the plurality of process steps into the memory, performing a tool commonality analysis on each of the tools associated with the at least one of the plurality of process steps, identifying all tool-to-tool differences for the at least one of the plurality of process steps, performing a tool stratification analysis to identify one of the plurality of tools that provides the largest variance contribution to the at least one of the plurality of process steps, and stopping the one of the plurality of tools that provides the largest variance contribution to the at least one of the plurality of process steps.
摘要翻译：分析生产步骤的方法包括将与具有多个处理步骤的生产过程相关联的应用数据输入存储器，其中多个处理步骤中的每一个包括多个工具。该方法还包括将与多个处理步骤之一相关联的过程数据加载到存储器中，对与多个处理步骤中的至少一个相关联的每个工具执行工具共性分析，识别所有工具对工具对于所述多个处理步骤中的至少一个处理步骤的差异，执行工具分层分析以识别为所述多个处理步骤中的至少一个处理步骤提供最大变化贡献的所述多个工具之一，并且停止多个工具，其对多个处理步骤中的至少一个提供最大的方差贡献。

5. 发明授权

US07682842B2 Method of adaptively selecting chips for reducing in-line testing in a semiconductor manufacturing line 失效
标题翻译：自适应选择芯片以减少半导体生产线中的在线测试的方法
公开(公告)号：US07682842B2
公开(公告)日：2010-03-23
申请号：US12129712
申请日：2008-05-30
申请人： Rao H. Desineni , Xu Ouyang , Hargurpreet Singh , Yunsheng Song , Stephen Wu
发明人： Rao H. Desineni , Xu Ouyang , Hargurpreet Singh , Yunsheng Song , Stephen Wu
IPC分类号： H01L21/00
CPC分类号： G01R31/2894
摘要： A method for identifying potentially defective integrated circuit chips and excluding them from future testing as wafers move through a manufacturing line The method includes data-collecting steps, tagging the chips on wafers identified as potentially bad chips based on information collected as the wafer moves down the fabrication line, evaluating test cost savings by eliminating any further tests on the tagged chips preferably using a test cost database. Considering all the future tests to be preformed, the tagged chips are skipped if it is determined that the test cost saving is significant. Tagging bad chips is based on various criteria and models which are dynamically adjusted by performing the wafer final test on samples of the tagged chips and feeding-back the final test results. The dynamic adaptive adjustment method preferably includes a feedback loop or iterative process to evaluate financial tradeoffs when assessing the profit of salvaging chips against the additional test costs.
摘要翻译：一种用于识别潜在有缺陷的集成电路芯片的方法，并将其从将来的测试中排除，因为晶片移动通过生产线。该方法包括数据收集步骤，基于当晶片向下移动时收集的信息将标记为潜在的坏芯片的晶片上的芯片标记通过消除对标记芯片的任何进一步测试，优选使用测试成本数据库来评估测试成本节省。考虑到将要执行的所有将来的测试，如果确定测试成本节省是重要的，则标记的芯片被跳过。标记坏芯片是基于各种标准和模型，通过对标记芯片的样品进行晶圆最终测试并反馈最终测试结果来动态调整。动态自适应调整方法优选地包括反馈循环或迭代过程，以在评估补救筹码的利润与额外的测试成本时评估金融权衡。

6. 发明申请

US20090143999A1 REAL TIME SYSTEM FOR MONITORING THE COMMONALITY, SENSITIVITY, AND REPEATABILITY OF TEST PROBES 失效
标题翻译：用于监测测试问题的共同性，敏感性和可重复性的实时系统
公开(公告)号：US20090143999A1
公开(公告)日：2009-06-04
申请号：US11950123
申请日：2007-12-04
申请人： Muthukumarasamy Karthikeyan , Louis V. Medina , Yunsheng Song , Tso-Hui Ting , Ping-Chuan Wang
发明人： Muthukumarasamy Karthikeyan , Louis V. Medina , Yunsheng Song , Tso-Hui Ting , Ping-Chuan Wang
IPC分类号： G01R31/26 , G06F19/00
CPC分类号： G01R31/2894 , G01R31/2886 , G01R35/005
摘要： A system and a method for effectively determining the measurement sensitivity, repeatability, and probe commonality to assist a test engineer determine if the tester meets the specified resolution at every test. A statistical measurement of inherent tester specifications are provided with the added accumulation of the probe contact resistance during the probing process. It further provides a feedback to the test probe card noise level while testing is in progress. Moreover, the system and the method determine the test probing integrity in-situ when testing integrated circuit chips or wafers, dynamically detecting probing errors, and modifying data associated with defective test probes.
摘要翻译：一种用于有效确定测量灵敏度，重复性和探头共性以帮助测试工程师确定测试仪是否在每次测试时满足指定分辨率的系统和方法。在探测过程中，增加了探针接触电阻的积累，对固有的测试仪规格进行统计测量。它进一步提供测试探针卡噪声水平的反馈。此外，系统和方法在测试集成电路芯片或晶圆时动态地检测探测误差以及修改与有缺陷的测试探针有关的数据，从而在现场确定测试探测完整性。

7. 发明申请

US20090119357A1 ADVANCED CORRELATION AND PROCESS WINDOW EVALUATION APPLICATION 审中-公开
标题翻译：先进的关联和过程窗口评估应用
公开(公告)号：US20090119357A1
公开(公告)日：2009-05-07
申请号：US11934914
申请日：2007-11-05
申请人： James P. Rice , Yunsheng Song , Yun-Yu Wang , Chienfan Yu
发明人： James P. Rice , Yunsheng Song , Yun-Yu Wang , Chienfan Yu
IPC分类号： G06F17/15
CPC分类号： G06K9/6253
摘要： A method only has the user input (or select) a data type, a report key, a dependent variable table, and/or filtering restrictions. Using this information, the method automatically locates independent variable data based on the data type and the report key. This independent variable data can be in the form of a table and comprises independent variables. The method automatically joins the dependent variable table and the independent variable data to create a joint table. Then, the method can automatically perform a statistical analysis of the joint table to find correlations between the dependent variables and the independent variables and output the correlations, without requiring the user to input or identify the independent variables.
摘要翻译：方法只有用户输入（或选择）数据类型，报告键，因变量表和/或过滤限制。使用该信息，该方法根据数据类型和报告密钥自动定位独立的变量数据。这个独立的变量数据可以是一个表格的形式，并且包括自变量。该方法自动连接因变量表和独立变量数据以创建联合表。然后，该方法可以自动执行联合表的统计分析，以找出因变量和独立变量之间的相关性，并输出相关性，而不需要用户输入或识别自变量。

8. 发明授权

US07337033B1 Data mining to detect performance quality of tools used repetitively in manufacturing 失效
标题翻译：数据挖掘来检测在制造过程中重复使用的工具的性能质量
公开(公告)号：US07337033B1
公开(公告)日：2008-02-26
申请号：US11460723
申请日：2006-07-28
申请人： Viorel Ontalus , Jeong Woo Nam , Yunsheng Song
发明人： Viorel Ontalus , Jeong Woo Nam , Yunsheng Song
IPC分类号： G06F19/00
CPC分类号： G05B19/41875 , G05B2219/32196 , G05B2219/32201 , G05B2219/45031 , Y02P90/22
摘要： A tool with one or more chambers in a manufacturing system is identified as performing at or below an acceptable level by the following steps. Store process data from tools for each one of a plurality of individual processes for a processed object in a process database. Store tool performance data for each individual process for a processed object in a yield database. Develop statistics for similar tool sets associating data with each of the similar tool units. Generate yield numbers for each group of the similar tool units based upon the statistics. Identify poorly/well performing tool units by using the yield numbers.
摘要翻译：在制造系统中具有一个或多个室的工具通过以下步骤被识别为执行在或低于可接受水平。存储过程数据库中处理对象的多个单独进程中的每一个的工具的过程数据。存储生产数据库中处理对象的每个进程的工具性能数据。开发用于将数据与每个相似工具单元相关联的类似工具集的统计信息。根据统计数据，为每组类似的工具单元生成产量编号。通过使用产量编号识别不良/性能良好的工具单位。

9. 发明授权

US08429193B2 Security control of analysis results 失效
标题翻译：分析结果的安全控制
公开(公告)号：US08429193B2
公开(公告)日：2013-04-23
申请号：US12351412
申请日：2009-01-09
申请人： Yunsheng Song , Tso-Hui Ting , Brian M. Trapp
发明人： Yunsheng Song , Tso-Hui Ting , Brian M. Trapp
IPC分类号： G06F17/30
CPC分类号： H04L63/0227 , G06F21/6218 , G06F2221/2141 , H04L63/102
摘要： A system and a method are provided. The method includes assigning an entity to a ticket group associated with an ID thereof, displaying to the entity reports, which are each organized with an associated security access control, in accordance with the ticket group, determining whether the entity is authorized to access any selected one or more of the reports in accordance with a result of a comparison between an access level associated with the entity ID and the security access control associated with each of the one or more of the stored reports, and granting or denying the access in accordance with the determination.
摘要翻译：提供了一种系统和方法。该方法包括将实体分配给与其ID相关联的票据组，根据票组显示实体报告，每个报告按相关联的安全访问控制进行组织，确定实体是否被授权访问任何所选择的根据与实体ID相关联的访问级别与与所存储的一个或多个报告中的每一个相关联的安全访问控制之间的比较的结果的一个或多个报告，以及根据决心。

10. 发明授权

US08159247B2 Yield enhancement for stacked chips through rotationally-connecting-interposer 有权
标题翻译：通过旋转连接插入器对堆叠芯片的产量提高
公开(公告)号：US08159247B2
公开(公告)日：2012-04-17
申请号：US12574264
申请日：2009-10-06
申请人： Oleg Gluschenkov , Muthukumarasamy Karthikeyan , Yunsheng Song , Tso-Hui Ting , Richard P. Volant , Ping-Chuan Wang
发明人： Oleg Gluschenkov , Muthukumarasamy Karthikeyan , Yunsheng Song , Tso-Hui Ting , Richard P. Volant , Ping-Chuan Wang
IPC分类号： G01R31/20
CPC分类号： G01R1/07378 , H01L22/14 , H01L22/20 , H01L25/50 , H01L2225/06596 , H01L2924/0002 , H01L2924/00
摘要： A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i−1)/N×2π. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield.
摘要翻译：一组第一衬底和第二衬底被制造成围绕每个衬底的中心轴线具有内置的N倍旋转对称，其中N是大于1的整数。提供一组N个不同的插入件，（i-1）/ N×2＆pgr的转角提供第一基板和第二基板之间的电连接。测试第一和第二衬底中的每个N个不同的插入件。一旦确定了提供最高堆叠芯片产量的旋转角度，则可以以提供最高堆叠芯片产量的方位角旋转来接合第一和第二基板。

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