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1. 发明授权

US5138709A Spurious interrupt monitor 失效
标题翻译：杂散中断监视器
公开(公告)号：US5138709A
公开(公告)日：1992-08-11
申请号：US508214
申请日：1990-04-11
申请人： Randall L. Jones , Mark R. Heene , Mark W. McDermott
发明人： Randall L. Jones , Mark R. Heene , Mark W. McDermott
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/0745 , G06F11/0751
摘要： In a microprocessor system including arbitration for an interrupt, an apparatus and method for monitoring the arbitration lines to determine whether an interrupt request is real or spurious is includued. Once an interrupt acknowledge signal is provided, the interrupting apparatus must arbitrate for the interrupt slot. If no arbitration occurs the interrupt request was spurious and bus error is activated.
摘要翻译：在包括用于中断的仲裁的微处理器系统中，包括用于监视仲裁线以确定中断请求是真实还是假的中断的装置和方法。一旦中断确认信号被提供，中断装置必须仲裁中断插槽。如果没有发生仲裁，则中断请求是虚假的，总线错误被激活。

2. 发明授权

US5592107A Configurable NAND/NOR element 失效
标题翻译：可配置NAND / NOR元件
公开(公告)号：US5592107A
公开(公告)日：1997-01-07
申请号：US497491
申请日：1995-06-30
申请人： Mark W. McDermott , John E. Turner
发明人： Mark W. McDermott , John E. Turner
IPC分类号： H03K19/173 , H03K19/0948
CPC分类号： H03K19/1736
摘要： A configurable NAND/NOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The NAND/NOR logic element (FIG. 3, 50) is configurable as either a NAND or a NOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). C inputs control p- and n-channel transistors. Depending on whether the C input is deasserted or asserted, respective internal nodes are shorted to effect the selected configuration. Specifically, deasserting C provides the NAND configuration, while asserting C provides the NOR configuration. In an alternative embodiment, the NAND/NOR logic element can be used in a full adder to provide the carry output.
摘要翻译：在示例性实施例中，在包括在处理器或其他集成电路中的备用阵列阵列中使用可配置NAND / NOR逻辑元件。 NAND / NOR逻辑元件（图3,50）可通过C（配置）输入（可以被金属可配置为被断言或无效）配置为NAND或NOR门。 C输入控制p沟道晶体管和n沟道晶体管。取决于C输入是否被断言或断言，相应的内部节点被短路以实现所选择的配置。具体来说，解锁C提供NAND配置，而断言C提供NOR配置。在替代实施例中，NAND / NOR逻辑元件可用于全加器以提供进位输出。

3. 发明授权

US5815692A Distributed clock generator 失效
标题翻译：分布式时钟发生器
公开(公告)号：US5815692A
公开(公告)日：1998-09-29
申请号：US572947
申请日：1995-12-15
申请人： Mark W. McDermott
发明人： Mark W. McDermott
IPC分类号： G06F1/10 , G06F1/06
CPC分类号： G06F1/10
摘要： A processor includes a distributed clock generator employing a plurality of independently adjustable clocks reconstituted locally from multiple signals. A centralized generator is disposed substantially in the middle of the processing system with satellite reconstitutors being disposed around the periphery to service various functional units which collectively manifest the processing system. The distribution of the multiple signals to the satellite reconstitutors provides substantially equal wire length and local reconstitution mitigates R-C time constant skew problems.
摘要翻译：处理器包括采用从多个信号本地重构的多个可独立调节的时钟的分布式时钟发生器。集中式发电机基本上设置在处理系统的中间，卫星重构器围绕周边设置，以便为共同显示处理系统的各种功能单元提供服务。多个信号到卫星重构器的分布提供了基本相等的线长度，并且局部重构减轻了R-C时间常数偏斜问题。

4. 发明授权

US5157781A Data processor test architecture 失效
标题翻译：数据处理器测试架构
公开(公告)号：US5157781A
公开(公告)日：1992-10-20
申请号：US459484
申请日：1990-01-02
申请人： Wallace B. Harwood , Mark W. McDermott , Dennis K. Verbeek
发明人： Wallace B. Harwood , Mark W. McDermott , Dennis K. Verbeek
IPC分类号： G01R31/317 , G01R31/3185 , G06F11/267
CPC分类号： G06F11/2236 , G01R31/31701 , G01R31/318505 , G06F11/2221
摘要： A test architecture in a data processing system having a plurality of circuit portions, coupled via a communication bus. In the system, a dedicated test register is placed in predetermined circuit portions which each can then operate in a normal mode and a test mode. A central processing unit (CPU) may initiate a test operation in any of the circuit portions in response to software executing by writing an operand to a centralized test module. Operands are scanned into and out of a circuit portion being tested while the central processing unit is capable of performing non-test processing activites. The CPU may also test itself using a dedicated test register which can only cause the CPU to enter a test mode after the register is written to.
摘要翻译：具有通过通信总线耦合的多个电路部分的数据处理系统中的测试架构。在该系统中，将专用测试寄存器放置在预定的电路部分中，每个电路部分可以在正常模式和测试模式下操作。中央处理单元（CPU）可以响应于通过将操作数写入集中式测试模块来执行软件来启动任何电路部分中的测试操作。当中央处理单元能够执行非测试处理活动时，操作数被扫描进出被测试的电路部分。 CPU也可以使用专用测试寄存器进行测试，该寄存器只能在寄存器写入后才能使CPU进入测试模式。

5. 发明授权

US5815693A Processor having a frequency modulated core clock based on the criticality of program activity 失效
标题翻译：处理器具有基于节目活动关键性的调频核心时钟
公开(公告)号：US5815693A
公开(公告)日：1998-09-29
申请号：US572994
申请日：1995-12-15
申请人： Mark W. McDermott , Antone L. Fourcroy
发明人： Mark W. McDermott , Antone L. Fourcroy
IPC分类号： G06F1/08 , G06F1/32 , G06F1/04
CPC分类号： G06F1/324 , G06F1/08 , G06F1/32 , Y02B60/1217
摘要： A processing system includes a clock synchromesh that receives indicia of critical activity from various functional units within the processing system and responsive to the indicia, ratchets down/up the frequency of a clock output signal to at least one of the functional units to reduce power consumption. The determination of critical activity is preferably made according to a heuristic internal to a processor under software or hardware control.
摘要翻译：一种处理系统包括时钟同步信号，其接收来自处理系统内的各个功能单元的关键活动的标记并且响应于该标记，将时钟输出信号的频率向上/向下升降至至少一个功能单元以降低功耗。关键活动的确定优选根据软件或硬件控制下处理器内部的启发式进行。

6. 发明授权

US5734881A Detecting short branches in a prefetch buffer using target location information in a branch target cache 失效
标题翻译：使用分支目标缓存中的目标位置信息检测预取缓冲区中的短分支
公开(公告)号：US5734881A
公开(公告)日：1998-03-31
申请号：US572773
申请日：1995-12-15
申请人： Christopher E. White , Antone L. Fourcroy , Mark W. McDermott
发明人： Christopher E. White , Antone L. Fourcroy , Mark W. McDermott
IPC分类号： G06F9/38
CPC分类号： G06F9/3812 , G06F9/30054 , G06F9/3806 , G06F9/3814
摘要： A pipelined x86 processor includes a prefetch unit (prefetch buffer) and a branch unit that cooperate to detect when the target of a branch (designated a short branch) is already in the prefetch buffer, thereby avoiding issuing a prefetch request to retrieve the target. The branch unit includes a branch target cache (BTC) in which each entry stores, in addition to target address information for prefetching a prefetch block of instruction bytes containing a target instruction, a prefetch block location field--when this field is valid, it provides the location of the target instruction for a short branch within a prefetch block that is already in the prefetch buffer. In response to a branch that hits in the BTC, if the associated prefetch block location field is valid, the prefetch unit is able to begin transferring instruction bytes for the target instruction without issuing a prefetch request for the prefetch block containing the target instruction. The exemplary prefetch unit uses a three-block prefetch buffer each storing a 16 byte (cache line) prefetch block--the three prefetch buffers are logically allocated for the current, next, and previous prefetch blocks, and the target of a short branch may be either forward or backward of the branch, and may reside in the same prefetch buffer as the branch (which logically will be current) or in a contiguous prefetch buffer (logically next or previous). Avoiding prefetch requests in the case of short branches reduces contention for cache access and associated bus traffic.
摘要翻译：流水线x86处理器包括预取单元（预取缓冲器）和协作以检测分支目标（指定为短分支）何时已经在预取缓冲器中的分支单元，从而避免发出预取请求以检索目标。分支单元包括分支目标高速缓存（BTC），除了用于预取包含目标指令的指令字节的预取块的目标地址信息之外，每个条目还存储预取块位置字段 - 当该字段有效时，其提供在预取块中已经在预取缓冲器中的短分支的目标指令的位置。响应于在BTC中击中的分支，如果相关联的预取块位置字段有效，则预取单元能够开始传送用于目标指令的指令字节，而不对包含目标指令的预取块发出预取请求。示例性预取单元使用三块预取缓冲器，每个存储16字节（高速缓存线）预取块 - 三个预取缓冲器在逻辑上分配给当前，下一个和先前的预取块，并且短分支的目标可以是分支的前向或后向，并且可以驻留在与分支（逻辑上将是当前）相同的预取缓冲器中，或者在连续的预取缓冲器（逻辑上是下一个或前一个）中。在短分支的情况下避免预取请求减少了缓存访问和相关总线流量的争用。

7. 发明授权

US5568067A Configurable XNOR/XOR element 失效
标题翻译：可配置的XNOR / XOR元素
公开(公告)号：US5568067A
公开(公告)日：1996-10-22
申请号：US497007
申请日：1995-06-30
申请人： Mark W. McDermott , John E. Turner
发明人： Mark W. McDermott , John E. Turner
IPC分类号： H03K19/173 , H03K19/21 , H03K19/094
CPC分类号： H03K19/215 , H03K19/1736
摘要： A configurable XNOR/XOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The XNOR/XOR logic element (FIG. 4, 60) is configurable as either an XNOR or an XOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). Inverted and noninverted C inputs control two coupling circuits: (a) coupling circuit C10 includes p-transistors C11, C12, C13, and C14, and (b) coupling circuit C20 includes n-transistors C21, C22, C23, and C24. Depending on whether the C input is deasserted or asserted (and the inverted C input is correspondingly asserted or deasserted), these configuration transistors series or cross couple parallel stacked p- and n-transistors that receive inverted and noninverted A and B inputs to effect the selected configuration. Specifically, deasserting C provides the XOR configuration, while asserting C provides the XNOR configuration. In an alternative embodiment, the XNOR/XOR logic element can be used in a full adder to provide the sum output.
摘要翻译：在示例性实施例中，在包括在处理器或其他集成电路中的备用阵列阵列中使用可配置的XNOR / XOR逻辑元件。 XNOR / XOR逻辑元件（图4，60）可以通过C（配置）输入（可以被金属可配置为被断言或无效）来配置为XOR或XOR门。反相和非反相C输入控制两个耦合电路：（a）耦合电路C10包括p晶体管C11，C12，C13和C14，（b）耦合电路C20包括n晶体管C21，C22，C23和C24。取决于C输入是否被断言或置为有效（并且反相C输入被相应地置为或无效），这些配置晶体管串联或交叉耦合并联堆叠的p型和n型晶体管，其接收反相和非反相的A和B输入以实现选择配置。具体来说，取消分配C提供XOR配置，而断言C提供XNOR配置。在替代实施例中，XNOR / XOR逻辑元件可用于全加器以提供和输出。

8. 发明授权

US5740410A Static clock generator 失效
标题翻译：静态时钟发生器
公开(公告)号：US5740410A
公开(公告)日：1998-04-14
申请号：US573172
申请日：1995-12-15
申请人： Mark W. McDermott
发明人： Mark W. McDermott
IPC分类号： G06F1/10 , G06F1/08
CPC分类号： G06F1/10
摘要： A processing system includes clock circuitry that statically multiplies/divides a stimulus signal which can then be removed while a resultant product clock is still generated, A cascaded--dual tap delay line is employed having a single phase inversion which is looped back and logically ORed with the first edge of the stimulus signal to induce oscillation. A multiplier/divisor control signal adjusts the "N" times multiplication by disabling the loop after the desired number of pulses is achieved within the period of the stimulus signal. 1/M multiplication is achieved by disabling the loop from oscillating for M stimulus clocks. Multiple frequencies can be dynamically realized on-the-fly without resynchronization by combining delayed clock pulses with a multiplexer.
摘要翻译：一种处理系统包括静态乘法/除法激励信号的时钟电路，然后在产生的产物时钟仍然产生的同时可以去除激励信号。采用级联双抽头延迟线，其具有环回和逻辑或刺激信号的第一个边缘引起振荡。乘数/除数控制信号通过在刺激信号的周期内实现所需数量的脉冲之后禁用环路来调整“N”次乘法。通过禁止M个激励时钟的振荡来实现1 / M乘法。通过将延迟的时钟脉冲与多路复用器组合，可以在运行时动态实现多个频率，而无需重新同步。

9. 发明授权

US5233314A Integrated charge-pump phase-locked loop circuit 失效
标题翻译：集成电荷泵锁相环电路
公开(公告)号：US5233314A
公开(公告)日：1993-08-03
申请号：US959522
申请日：1992-10-13
申请人： Mark W. McDermott , Richard B. Reis
发明人： Mark W. McDermott , Richard B. Reis
IPC分类号： H03L7/089 , H03L7/093 , H03L7/099 , H03L7/107
CPC分类号： H03L7/0898 , H03L7/0995 , H03L7/107 , H03L7/093
摘要： A variable bandwidth phase-locked loop clock generator circuit is disclosed. The PLL circuit includes a phase comparator which presents pump-up and pump-down signals, indicating the polarity of the desired frequency change. The phase comparator also generates multiple level control outputs to control the rate of the frequency change. A current source includes a reference leg having a plurality of resistors which are shorted out according to the control outputs, from which a bias signal is generated. The level of the bias signal controls current sources in the output leg of the current source to control the rate of change of the voltage applied to the voltage controlled oscillator. In addition, the bias signal also controls the slew rate of an active low-pass filter according to the desired response characteristic; the output of the filter is applied to the voltage controlled oscillator for generating the output clock signal. This construction of the PLL circuit allows for the control signals to control the rate of change both for advancing and retarding the output clock frequency, and allows for on-chip implementation of the filter components in a manner compatible with MOS technology.
摘要翻译：公开了一种可变带宽锁相环时钟发生器电路。 PLL电路包括相位比较器，其提供泵浦和抽吸信号，指示所需频率变化的极性。相位比较器还产生多个电平控制输出以控制频率变化的速率。电流源包括具有根据控制输出短路的多个电阻器的参考支线，从该电源产生偏置信号。偏置信号的电平控制电流源的输出支路中的电流源，以控制施加到压控振荡器的电压的变化率。此外，偏置信号还根据期望的响应特性来控制有源低通滤波器的转换速率; 滤波器的输出被施加到压控振荡器以产生输出时钟信号。 PLL电路的这种结构允许控制信号控制用于提前和延迟输出时钟频率的变化率，并且允许以与MOS技术兼容的方式片上实现滤波器组件。

10. 发明授权

US4959561A MOS output buffer with reduced supply line disturbance 失效
标题翻译： MOS输出缓冲器具有减少的电源线干扰
公开(公告)号：US4959561A
公开(公告)日：1990-09-25
申请号：US499569
申请日：1990-03-26
申请人： Mark W. McDermott , Ernest A. Carter
发明人： Mark W. McDermott , Ernest A. Carter
IPC分类号： G11C7/10 , H03K19/003
CPC分类号： H03K19/00361 , G11C7/1051
摘要： An output buffer with reduced supply line disturbance is provided for use in high performance microprocessor circuits. The output buffer uses a resistor and transistor as a sensing circuit, in parallel with an output driver transistor, thereby providing a negative feedback path into the control circuitry for the output driver. The sensing circuit detects the strength of the output driver transistor, by monitoring the amount of capacitance on the output node when the output buffer is driving the output signal to a logic high or logic low state, and rapidly produces a control voltage. The current flowing through the driver transistor and the sensor transistor causes a voltage drop across the resistor, which is fedback into the control circuitry. The control voltage is fed back into the output buffer control circuitry, thereby facilitating the reduction of the current drive capabilities of the driver and sensor transistors. Thus, the control circuitry reduces the change in current flow (di/dt) attributable to the operation of the driver and sensor transistors during the output buffer logic state transition.
摘要翻译：提供具有减少的电源线干扰的输出缓冲器用于高性能微处理器电路。输出缓冲器使用电阻和晶体管作为与输出驱动晶体管并联的感测电路，从而为输出驱动器提供用于控制电路的负反馈路径。当输出缓冲器将输出信号驱动到逻辑高或逻辑低电平状态时，感测电路通过监视输出节点上的电容量来检测输出驱动晶体管的强度，并快速产生控制电压。流过驱动晶体管和传感器晶体管的电流导致电阻上的电压降，反馈到控制电路。控制电压被反馈到输出缓冲器控制电路中，从而有助于降低驱动器和传感器晶体管的电流驱动能力。因此，控制电路减少了在输出缓冲器逻辑状态转换期间归因于驱动器和传感器晶体管的操作的电流（di / dt）的变化。

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