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1. 发明授权

US06376389B1 Method for eliminating anti-reflective coating in semiconductors 有权
标题翻译：消除半导体抗反射涂层的方法
公开(公告)号：US06376389B1
公开(公告)日：2002-04-23
申请号：US09588117
申请日：2000-05-31
申请人： Ramkumar Subramanian , Minh Van Ngo , Kashmir Sahota , Yongzhong Hu , Hiroyuki Kinoshita , Fei Wang , Wenge Yang
发明人： Ramkumar Subramanian , Minh Van Ngo , Kashmir Sahota , Yongzhong Hu , Hiroyuki Kinoshita , Fei Wang , Wenge Yang
IPC分类号： H01L2100
CPC分类号： H01L21/76802 , H01L21/76895 , H01L23/522 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a semiconductor device without the use of an anti-reflective coating. In one embodiment, electrical devices are formed on a semiconductor substrate. A material with a low dielectric constant such as an oxide is then deposited. The low dielectric layer is then covered with photoresist and photolithographically processed and subsequently developed. The low dielectric layer is then etched using the pattern formed on the photoresist and the photoresist is later removed. Because this process works in any similar circumstances, good examples of its application are the formation of both contacts and local interconnects.
摘要翻译：本发明提供一种不使用抗反射涂层的半导体器件的制造方法。在一个实施例中，电子器件形成在半导体衬底上。然后沉积具有低介电常数的材料，例如氧化物。然后用光致抗蚀剂覆盖低介电层，并进行光刻处理并随后显影。然后使用形成在光致抗蚀剂上的图案蚀刻低介电层，随后去除光致抗蚀剂。因为这个过程在任何类似的情况下都可以工作，它的应用的很好的例子是形成两个触点和局部互连。

2. 发明授权

US06348406B1 Method for using a low dielectric constant layer as a semiconductor anti-reflective coating 有权
标题翻译：使用低介电常数层作为半导体抗反射涂层的方法
公开(公告)号：US06348406B1
公开(公告)日：2002-02-19
申请号：US09586264
申请日：2000-05-31
申请人： Ramkumar Subramanian , Minh Van Ngo , Kashmir Sahota , Yongzhong Hu , Hiroyuki Kinoshita , Fei Wang , Wenge Yang
发明人： Ramkumar Subramanian , Minh Van Ngo , Kashmir Sahota , Yongzhong Hu , Hiroyuki Kinoshita , Fei Wang , Wenge Yang
IPC分类号： H01L214763
CPC分类号： H01L27/11521 , H01L21/31144
摘要： The present invention provides a method for manufacturing a semiconductor device with an anti-reflective coating (ARC) that does not need to be removed. In one embodiment, electrical devices are formed on a semiconductor substrate. A dielectric layer is then deposited over the electrical devices and the semiconductor substrate, upon which an optically transparent ARC layer of low dielectric constant is then deposited. Photoresist is then deposited on top of the ARC layer and is then photolithographically processed and subsequently developed. The dielectric layer is then etched down to the semiconductor substrate to form contacts or local interconnects. The ARC layer can subsequently be used as a hard mask and does not require removal.
摘要翻译：本发明提供一种制造具有不需要去除的抗反射涂层（ARC）的半导体器件的方法。在一个实施例中，电子器件形成在半导体衬底上。然后将电介质层沉积在电气器件和半导体衬底上，然后沉积出具有低介电常数的光学透明ARC层。然后将光致抗蚀剂沉积在ARC层的顶部上，然后光刻加工并随后显影。然后将电介质层向下蚀刻到半导体衬底以形成接触或局部互连。 ARC层可以随后用作硬掩模，并且不需要去除。

3. 发明授权

US06482699B1 Method for forming self-aligned contacts and local interconnects using decoupled local interconnect process 有权
标题翻译：使用去耦局部互连过程形成自对准触点和局部互连的方法
公开(公告)号：US06482699B1
公开(公告)日：2002-11-19
申请号：US09685972
申请日：2000-10-10
申请人： YongZhong Hu , Fei Wang , Wenge Yang , Yu Sun , Ramkumar Subramanian
发明人： YongZhong Hu , Fei Wang , Wenge Yang , Yu Sun , Ramkumar Subramanian
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L21/76895 , H01L2924/3011
摘要： A method of manufacturing a semiconductor device is provided in which multi-layer structures are formed on a semiconductor substrate to form core and peripheral regions. Sidewall spacers are formed around the multi-layer structures and source and drain regions are implanted adjacent the sidewall spacers and a stop layer is deposited over the semiconductor substrate after which a dielectric layer is deposited over the stop layer. A first and second photoresist contact masks are deposited, processed, and used to respectively etch core and peripheral contact openings. The first and photoresist contact masks are respectively removed after each etching step. A conductive material is deposited over the dielectric layer and in the core and peripheral contact openings and is chemical mechanical planarized to remove the conductive material over the dielectric layer so the conductive material is left isolated in the core and peripheral contact openings with core contacts to the source/drain regions and peripheral contacts to the local interconnect gate contacts of the multi-layer structures and the source/drain regions.
摘要翻译：提供一种制造半导体器件的方法，其中在半导体衬底上形成多层结构以形成芯和周边区域。在多层结构周围形成侧壁间隔物，并且将源极和漏极区域相邻于侧壁间隔物注入，并且在半导体衬底上沉积停止层，之后在停止层上沉积电介质层。第一和第二光致抗蚀剂接触掩模被沉积，处理并用于分别蚀刻芯部和外围接触开口。在每个蚀刻步骤之后分别去除第一和光致抗蚀剂接触掩模。导电材料沉积在电介质层上以及芯和外围接触开口中，并进行化学机械平面化以去除电介质层上的导电材料，因此导电材料在核心和外围接触开口中被隔离，其核心接触到源极/漏极区域和周边接触到多层结构和源极/漏极区域的局部互连栅极触点。

4. 发明授权

US06380067B1 Method for creating partially UV transparent anti-reflective coating for semiconductors 有权
标题翻译：半导体部分UV透明抗反射涂层的制造方法
公开(公告)号：US06380067B1
公开(公告)日：2002-04-30
申请号：US09588119
申请日：2000-05-31
申请人： Ramkumar Subramanian , Minh Van Ngo , Suzette K. Pangrle , Kashmir Sahota , Christopher F. Lyons
发明人： Ramkumar Subramanian , Minh Van Ngo , Suzette K. Pangrle , Kashmir Sahota , Christopher F. Lyons
IPC分类号： H01L21302
CPC分类号： H01L21/76895 , H01L21/0276 , H01L21/76802 , H01L27/105 , H01L27/11526 , H01L27/11534
摘要： The present invention provides a method for manufacturing a semiconductor device with a bottom anti-reflective coating (BARC) that acts as an etch stop layer and does not need to be removed. In one embodiment, electrical devices are formed on a semiconductor substrate. Contacts are then formed for each electrical device and a partially UV transparent BARC is then deposited. An inter-layer dielectric (ILD) layer is then formed and then covered with photoresist. A top ARC (TARC) is then added and the photoresist is then photolithographically processed and subsequently developed. The TARC, ILD, and BARC layers are then selectively etched down to the device contacts forming local interconnects. The photoresist and TARC are later removed, but the BARC does not require removal due to its optical transparency.
摘要翻译：本发明提供一种用于制造半导体器件的方法，该半导体器件具有用作蚀刻停止层并且不需要去除的底部抗反射涂层（BARC）。在一个实施例中，电子器件形成在半导体衬底上。然后为每个电气设备形成触点，然后沉积部分UV透明的BARC。然后形成层间电介质（ILD）层，然后用光致抗蚀剂覆盖。然后加入顶部ARC（TARC），然后对光致抗蚀剂进行光刻处理并随后显影。然后将TARC，ILD和BARC层选择性地刻蚀成形成局部互连的器件触点。光致抗蚀剂和TARC随后被去除，但由于其光学透明性，BARC不需要去除。

5. 发明授权

US06294460B1 Semiconductor manufacturing method using a high extinction coefficient dielectric photomask 有权
标题翻译：使用高消光系数电介质光掩模的半导体制造方法
公开(公告)号：US06294460B1
公开(公告)日：2001-09-25
申请号：US09586254
申请日：2000-05-31
申请人： Ramkumar Subramanian , Minh Van Ngo , Suzette K. Pangrle , Kashmir Sahota
发明人： Ramkumar Subramanian , Minh Van Ngo , Suzette K. Pangrle , Kashmir Sahota
IPC分类号： H01L214763
CPC分类号： H01L21/7688 , H01L21/76802 , Y10S438/952
摘要： A method is provided for manufacturing a semiconductor with fewer steps and minimized variation in the etching process by using SiON as a bottom antireflective (BARC) layer and hard mask in conjunction with a thin photoresist layer. In one embodiment, an etch-stop layer is deposited on a semiconductor substrate, a dielectric layer is deposited on top of the etch-stop layer, and a BARC is deposited on top of the dielectric layer. The BARC is deposited by PECVD to enrich the BARC with semiconductor material to increase the extinction coefficient of the BARC so its thickness can be reduced. A photoresist layer with a thickness less than the thickness of the BARC is then deposited on top of the BARC. The photoresist is then patterned, photolithographically processed, developed, and removed. The BARC is then etched away in the pattern developed on the photoresist and the photoresist is then removed. The BARC is then used as a mask for the etching of the dielectric layer. A conductive material is deposited over the BARC and the dielectric layer and is subsequently removed in the process of polishing the conductive material without requiring a separate BARC removal step.
摘要翻译：提供了一种通过使用SiON作为底部抗反射（BARC）层和与薄的光致抗蚀剂层结合的硬掩模来制造具有较少步骤和最小化蚀刻工艺的半导体的方法。在一个实施例中，蚀刻停止层沉积在半导体衬底上，电介质层沉积在蚀刻停止层的顶部，并且BARC沉积在电介质层的顶部上。 BARC通过PECVD沉积，以使BARC富集半导体材料，以增加BARC的消光系数，从而减小其厚度。然后将厚度小于BARC的厚度的光致抗蚀剂层沉积在BARC的顶部。然后将光致抗蚀剂图案化，光刻加工，显影和除去。然后将BARC以在光致抗蚀剂上显影的图案蚀刻掉，然后除去光致抗蚀剂。然后将BARC用作蚀刻电介质层的掩模。导电材料沉积在BARC和电介质层上，随后在抛光导电材料的过程中被去除，而不需要单独的BARC去除步骤。

6. 发明授权

US06878622B1 Method for forming SAC using a dielectric as a BARC and FICD enlarger 有权
标题翻译：使用电介质作为BARC和FICD放大器形成SAC的方法
公开(公告)号：US06878622B1
公开(公告)日：2005-04-12
申请号：US10612554
申请日：2003-07-01
申请人： Wenge Yang , Ramkumar Subramanian , Fei Wang , Lewis Shen
发明人： Wenge Yang , Ramkumar Subramanian , Fei Wang , Lewis Shen
IPC分类号： H01L21/027 , H01L21/311 , H01L21/60 , H01L21/4763 , H01L21/302 , H01L21/44
CPC分类号： H01L21/76897 , H01L21/0276 , H01L21/31116 , H01L2924/3011
摘要： A method is provided for manufacturing a semiconductor device on a semiconductor substrate using a dielectric as a bottom anti-reflective coating for formation of a photoresist contact opening which is used to enlarge the Final Inspection Critical Dimension (FICD) of the conductive contact. A high selectivity etch is used to form a tapered contact.
摘要翻译：提供了一种用于在半导体衬底上制造半导体器件的方法，该半导体衬底使用电介质作为用于形成光刻胶接触开口的底部抗反射涂层，用于扩大导电触点的最终检查临界尺寸（FICD）。使用高选择性蚀刻来形成锥形接触。

7. 发明授权

US06656763B1 Spin on polymers for organic memory devices 失效
标题翻译：旋转有机存储器件的聚合物
公开(公告)号：US06656763B1
公开(公告)日：2003-12-02
申请号：US10385375
申请日：2003-03-10
申请人： Jane V. Oglesby , Christopher F. Lyons , Ramkumar Subramanian , Angela T. Hui , Minh Van Ngo , Suzette K. Pangrle
发明人： Jane V. Oglesby , Christopher F. Lyons , Ramkumar Subramanian , Angela T. Hui , Minh Van Ngo , Suzette K. Pangrle
IPC分类号： H01L5140
CPC分类号： G11C13/025 , B82Y10/00 , G11C11/5664 , G11C13/0014 , G11C13/0016 , G11C2213/16 , G11C2213/71 , H01L27/285 , H01L51/0003 , H01L51/0004 , H01L51/0034 , H01L51/0035 , H01L51/0036 , H01L51/0037 , H01L51/0038 , H01L51/0041 , H01L51/005 , H01L51/0053 , H01L51/0059 , H01L51/0062 , H01L51/0077 , H01L51/0078 , H01L51/0081 , H01L51/0084 , H01L51/0085 , Y10S977/843 , Y10S977/944
摘要： A method of making organic memory cells made of two electrodes with a controllably conductivce media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer and passive layer. The organic semiconductor layer is formed using spin-on techniques with the assistance of certain solvents.
摘要翻译：公开了一种在两个电极之间制造具有可控导电介质的两个电极制成的有机存储单元的方法。可控导电介质包含有机半导体层和无源层。在某些溶剂的帮助下，使用旋转技术形成有机半导体层。

8. 发明授权

US06459155B1 Damascene processing employing low Si-SiON etch stop layer/arc 有权
标题翻译：使用低Si-SiON蚀刻停止层/电弧的镶嵌加工
公开(公告)号：US06459155B1
公开(公告)日：2002-10-01
申请号：US09729528
申请日：2000-12-05
申请人： Ramkumar Subramanian , Dawn M. Hopper , Minh Van Ngo
发明人： Ramkumar Subramanian , Dawn M. Hopper , Minh Van Ngo
IPC分类号： H01L214763
CPC分类号： H01L21/76829 , H01L21/0276 , H01L21/0332 , H01L21/76807
摘要： The dimensional accuracy of trench formation and, hence, metal line width, in damascene technology is improved by employing a low Si—SiON etch stop layer/ARC with reduced etch selectivity with respect to the overlying dielectric material but having a reduced extinction coefficient (k). Embodiments include via first-trench last dual damascene techniques employing a low Si—SiON middle etch stop layer/ARC having an extinction coefficient of about −0.3 to about −0.6, e.g., about −0.35, with reduced silicon and increased oxygen vis-à-vis a SiON etch stop layer having an extinction coefficient of about −1.1. Embodiments also include removing about 60% to about 90% of the low Si—SiON etch stop layer/ARC during trench formation, thereby reducing capacitance.
摘要翻译：通过使用低Si-SiON蚀刻停止层/ ARC，相对于上覆电介质材料具有降低的蚀刻选择性但具有降低的消光系数（k（k）），改善了镶嵌技术中沟槽形成的尺寸精度以及因此金属线宽度）。实施例包括通过第一沟槽最后的双镶嵌技术，其使用具有约-0.3至约-0.6，例如约-0.35的消光系数的低Si-SiON中间蚀刻停止层/ ARC，其中还原的硅和增加的氧相对于 - 具有约-1.1的消光系数的SiON蚀刻停止层。实施例还包括在沟槽形成期间去除约60％至约90％的低Si-SiON蚀刻停止层/ ARC，从而降低电容。

9. 发明授权

US06787458B1 Polymer memory device formed in via opening 失效
标题翻译：聚合物存储器件形成在通孔中
公开(公告)号：US06787458B1
公开(公告)日：2004-09-07
申请号：US10614397
申请日：2003-07-07
申请人： Nicholas H. Tripsas , Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Angela T. Hui , Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , Minh Van Ngo , Ashok M. Khathuria , Mark S. Chang , Patrick K. Cheung , Jane V. Oglesby
发明人： Nicholas H. Tripsas , Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Angela T. Hui , Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , Minh Van Ngo , Ashok M. Khathuria , Mark S. Chang , Patrick K. Cheung , Jane V. Oglesby
IPC分类号： H01L2144
CPC分类号： H01L27/285 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.
摘要翻译：本发明的一个方面涉及在通孔中制造聚合物存储器件的方法。该方法包括提供其上具有至少一个含金属层的半导体衬底，在含金属层中形成至少一个铜触点，在铜触点上形成至少一个电介质层，在电介质层中形成至少一个通孔露出铜触点的至少一部分，在通孔的下部形成聚合物材料，并在通孔的上部形成顶部电极材料层。

10. 发明授权

US06803267B1 Silicon containing material for patterning polymeric memory element 有权
标题翻译：含硅材料用于图案化聚合物记忆元件
公开(公告)号：US06803267B1
公开(公告)日：2004-10-12
申请号：US10614484
申请日：2003-07-07
申请人： Ramkumar Subramanian , Christopher F. Lyons , Matthew S. Buynoski , Patrick K. Cheung , Angela T. Hui , Ashok M. Khathuria , Sergey D. Lopatin , Minh Van Ngo , Jane V. Oglesby , Terence C. Tong , James J. Xie
发明人： Ramkumar Subramanian , Christopher F. Lyons , Matthew S. Buynoski , Patrick K. Cheung , Angela T. Hui , Ashok M. Khathuria , Sergey D. Lopatin , Minh Van Ngo , Jane V. Oglesby , Terence C. Tong , James J. Xie
IPC分类号： H01L21336
CPC分类号： H01L27/28 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L51/0018
摘要： The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, and operatively coupling the an upper electrode to the lower electrode through the organic semiconductor material and the passive material. Patterning of the organic semiconductor material is achieved by depositing a silicon-based resist over the organic semiconductor, irradiating portions of the silicon-based resist and patterning the silicon-based resist to remove the irradiated portions of the silicon-based resist. Thereafter, the exposed organic semiconductor can be patterned, and the non-irradiated silicon-based resist can be stripped to expose the organic semiconductor material that can be employed as a memory cell for single and multi-cell memory devices. A partitioning component can be integrated with the memory device to facilitate stacking memory devices and programming, reading, writing and erasing memory elements.
摘要翻译：本发明提供一种制造有机存储器件的方法，其中所述制造方法包括形成下电极，在所述下电极的表面上沉积无源材料，在所述被动材料上施加有机半导体材料，以及将所述有源半导体材料上电极通过有机半导体材料和被动材料到下电极。有机半导体材料的图案化是通过在有机半导体上沉积硅基抗蚀剂，照射硅基抗蚀剂的部分并图案化硅基抗蚀剂以除去硅基抗蚀剂的照射部分来实现的。此后，可以对暴露的有机半导体进行构图，并且可以剥离未照射的硅基抗蚀剂以暴露可用作单电池和多电池存储器件的存储器单元的有机半导体材料。分区组件可以与存储器件集成，以便于堆叠存储器件和编程，读取，写入和擦除存储器元件。

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