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1. 发明授权

US06482699B1 Method for forming self-aligned contacts and local interconnects using decoupled local interconnect process 有权
标题翻译：使用去耦局部互连过程形成自对准触点和局部互连的方法
公开(公告)号：US06482699B1
公开(公告)日：2002-11-19
申请号：US09685972
申请日：2000-10-10
申请人： YongZhong Hu , Fei Wang , Wenge Yang , Yu Sun , Ramkumar Subramanian
发明人： YongZhong Hu , Fei Wang , Wenge Yang , Yu Sun , Ramkumar Subramanian
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L21/76895 , H01L2924/3011
摘要： A method of manufacturing a semiconductor device is provided in which multi-layer structures are formed on a semiconductor substrate to form core and peripheral regions. Sidewall spacers are formed around the multi-layer structures and source and drain regions are implanted adjacent the sidewall spacers and a stop layer is deposited over the semiconductor substrate after which a dielectric layer is deposited over the stop layer. A first and second photoresist contact masks are deposited, processed, and used to respectively etch core and peripheral contact openings. The first and photoresist contact masks are respectively removed after each etching step. A conductive material is deposited over the dielectric layer and in the core and peripheral contact openings and is chemical mechanical planarized to remove the conductive material over the dielectric layer so the conductive material is left isolated in the core and peripheral contact openings with core contacts to the source/drain regions and peripheral contacts to the local interconnect gate contacts of the multi-layer structures and the source/drain regions.
摘要翻译：提供一种制造半导体器件的方法，其中在半导体衬底上形成多层结构以形成芯和周边区域。在多层结构周围形成侧壁间隔物，并且将源极和漏极区域相邻于侧壁间隔物注入，并且在半导体衬底上沉积停止层，之后在停止层上沉积电介质层。第一和第二光致抗蚀剂接触掩模被沉积，处理并用于分别蚀刻芯部和外围接触开口。在每个蚀刻步骤之后分别去除第一和光致抗蚀剂接触掩模。导电材料沉积在电介质层上以及芯和外围接触开口中，并进行化学机械平面化以去除电介质层上的导电材料，因此导电材料在核心和外围接触开口中被隔离，其核心接触到源极/漏极区域和周边接触到多层结构和源极/漏极区域的局部互连栅极触点。

2. 发明授权

US06348406B1 Method for using a low dielectric constant layer as a semiconductor anti-reflective coating 有权
标题翻译：使用低介电常数层作为半导体抗反射涂层的方法
公开(公告)号：US06348406B1
公开(公告)日：2002-02-19
申请号：US09586264
申请日：2000-05-31
申请人： Ramkumar Subramanian , Minh Van Ngo , Kashmir Sahota , Yongzhong Hu , Hiroyuki Kinoshita , Fei Wang , Wenge Yang
发明人： Ramkumar Subramanian , Minh Van Ngo , Kashmir Sahota , Yongzhong Hu , Hiroyuki Kinoshita , Fei Wang , Wenge Yang
IPC分类号： H01L214763
CPC分类号： H01L27/11521 , H01L21/31144
摘要： The present invention provides a method for manufacturing a semiconductor device with an anti-reflective coating (ARC) that does not need to be removed. In one embodiment, electrical devices are formed on a semiconductor substrate. A dielectric layer is then deposited over the electrical devices and the semiconductor substrate, upon which an optically transparent ARC layer of low dielectric constant is then deposited. Photoresist is then deposited on top of the ARC layer and is then photolithographically processed and subsequently developed. The dielectric layer is then etched down to the semiconductor substrate to form contacts or local interconnects. The ARC layer can subsequently be used as a hard mask and does not require removal.
摘要翻译：本发明提供一种制造具有不需要去除的抗反射涂层（ARC）的半导体器件的方法。在一个实施例中，电子器件形成在半导体衬底上。然后将电介质层沉积在电气器件和半导体衬底上，然后沉积出具有低介电常数的光学透明ARC层。然后将光致抗蚀剂沉积在ARC层的顶部上，然后光刻加工并随后显影。然后将电介质层向下蚀刻到半导体衬底以形成接触或局部互连。 ARC层可以随后用作硬掩模，并且不需要去除。

3. 发明授权

US06376389B1 Method for eliminating anti-reflective coating in semiconductors 有权
标题翻译：消除半导体抗反射涂层的方法
公开(公告)号：US06376389B1
公开(公告)日：2002-04-23
申请号：US09588117
申请日：2000-05-31
申请人： Ramkumar Subramanian , Minh Van Ngo , Kashmir Sahota , Yongzhong Hu , Hiroyuki Kinoshita , Fei Wang , Wenge Yang
发明人： Ramkumar Subramanian , Minh Van Ngo , Kashmir Sahota , Yongzhong Hu , Hiroyuki Kinoshita , Fei Wang , Wenge Yang
IPC分类号： H01L2100
CPC分类号： H01L21/76802 , H01L21/76895 , H01L23/522 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a semiconductor device without the use of an anti-reflective coating. In one embodiment, electrical devices are formed on a semiconductor substrate. A material with a low dielectric constant such as an oxide is then deposited. The low dielectric layer is then covered with photoresist and photolithographically processed and subsequently developed. The low dielectric layer is then etched using the pattern formed on the photoresist and the photoresist is later removed. Because this process works in any similar circumstances, good examples of its application are the formation of both contacts and local interconnects.
摘要翻译：本发明提供一种不使用抗反射涂层的半导体器件的制造方法。在一个实施例中，电子器件形成在半导体衬底上。然后沉积具有低介电常数的材料，例如氧化物。然后用光致抗蚀剂覆盖低介电层，并进行光刻处理并随后显影。然后使用形成在光致抗蚀剂上的图案蚀刻低介电层，随后去除光致抗蚀剂。因为这个过程在任何类似的情况下都可以工作，它的应用的很好的例子是形成两个触点和局部互连。

4. 发明授权

US06306713B1 Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer 有权
标题翻译：用于使用次级间隔件形成用于盐水门的自对准接触件和局部互连的方法
公开(公告)号：US06306713B1
公开(公告)日：2001-10-23
申请号：US09799469
申请日：2001-03-05
申请人： YongZhong Hu , Fei Wang , Wenge Yang , Yu Sun , Hiroyuki Kinoshita
发明人： YongZhong Hu , Fei Wang , Wenge Yang , Yu Sun , Hiroyuki Kinoshita
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L21/76895 , H01L2924/3011
摘要： A method of manufacturing a semiconductor device is provided in which multi-layer structures are formed on a semiconductor substrate to form core and peripheral regions. Sidewall spacers are formed around the multi-layer structures and source and drain regions are implanted adjacent the sidewall spacers. The multi-layer structures and the source and drain regions are silicided and a stop layer is deposited over the semiconductor substrate after which a dielectric layer is deposited over the stop layer. A photoresist contact mask is deposited, processed, and used to form core contact openings over the core region, which expose the multi-layer structure in addition to the source and drain regions while covering the peripheral region. Protective secondary sidewall spacers are formed in the core contact openings over the exposed multi-layer structures. A second photoresist contact mask is deposited, processed, and used to form peripheral local interconnect openings over the peripheral region which the source and drain regions and portions of the plurality of multi-layer structures in the peripheral region while covering the core region. A conductive material is deposited over the dielectric layer and in the core contact and peripheral local interconnect openings and is chemical mechanical planarized to remove the conductive material over the dielectric layer so the conductive material is left isolated in the core and peripheral contact openings.
摘要翻译：提供一种制造半导体器件的方法，其中在半导体衬底上形成多层结构以形成芯和周边区域。围绕多层结构形成侧壁间隔物，并且将源极和漏极区域相邻于侧壁间隔物注入。多层结构和源极和漏极区域被硅化，并且在半导体衬底上沉积停止层，之后在停止层上沉积电介质层。光致抗蚀剂接触掩模被沉积，加工并用于在芯部区域上形成芯接触开口，除了覆盖周边区域之外，还暴露多层结构以及源极和漏极区域。保护性次级侧壁间隔件形成在暴露的多层结构上的芯接触开口中。第二光致抗蚀剂接触掩模被沉积，加工并用于在外围区域上形成周边局部互连开口，周边区域是外围区域的源极和漏极区域以及多个多层结构的部分，同时覆盖芯部区域。导电材料沉积在电介质层上，并在芯接触和外围局部互连开口中沉积，并进行化学机械平面化以去除电介质层上的导电材料，使得导电材料在芯和外围接触开口中被隔离。

5. 发明授权

US06878622B1 Method for forming SAC using a dielectric as a BARC and FICD enlarger 有权
标题翻译：使用电介质作为BARC和FICD放大器形成SAC的方法
公开(公告)号：US06878622B1
公开(公告)日：2005-04-12
申请号：US10612554
申请日：2003-07-01
申请人： Wenge Yang , Ramkumar Subramanian , Fei Wang , Lewis Shen
发明人： Wenge Yang , Ramkumar Subramanian , Fei Wang , Lewis Shen
IPC分类号： H01L21/027 , H01L21/311 , H01L21/60 , H01L21/4763 , H01L21/302 , H01L21/44
CPC分类号： H01L21/76897 , H01L21/0276 , H01L21/31116 , H01L2924/3011
摘要： A method is provided for manufacturing a semiconductor device on a semiconductor substrate using a dielectric as a bottom anti-reflective coating for formation of a photoresist contact opening which is used to enlarge the Final Inspection Critical Dimension (FICD) of the conductive contact. A high selectivity etch is used to form a tapered contact.
摘要翻译：提供了一种用于在半导体衬底上制造半导体器件的方法，该半导体衬底使用电介质作为用于形成光刻胶接触开口的底部抗反射涂层，用于扩大导电触点的最终检查临界尺寸（FICD）。使用高选择性蚀刻来形成锥形接触。

6. 发明授权

US06359307B1 Method for forming self-aligned contacts and interconnection lines using dual damascene techniques 有权
标题翻译：使用双镶嵌技术形成自对准触点和互连线的方法
公开(公告)号：US06359307B1
公开(公告)日：2002-03-19
申请号：US09493436
申请日：2000-01-29
申请人： Fei Wang , Hiroyuki Kinoshita , Kashmir Sahota , Yu Sun , Wenge Yang
发明人： Fei Wang , Hiroyuki Kinoshita , Kashmir Sahota , Yu Sun , Wenge Yang
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L23/485 , H01L27/115 , H01L27/11521 , H01L2924/0002 , H01L2924/3011 , Y02P80/30 , H01L2924/00
摘要： The present invention further provides a method for forming self-aligned contacts using a dual damascene techniques that reduces the number of process steps and results in a reduction in cycle time, cost and yield loss. In a preferred embodiment, a method for forming a contact and a channel in a dielectric layer over a region on a semiconductor substrate is provided. The contact is self-aligned. The contact and channel are formed by (1) forming a contact opening in the dielectric layer, (2) forming a channel opening in the dielectric layer, wherein the channel opening encompasses the contact opening, (3) extending the contact opening to expose a portion of the region on the semiconductor substrate; and (4) filling the contact opening and the channel opening with a conductive material to form a contact and a channel, respectively.
摘要翻译：本发明还提供了一种使用双镶嵌技术形成自对准接触的方法，其减少了工艺步骤的数量并导致了循环时间，成本和屈服损失的降低。在优选实施例中，提供了在半导体衬底上的区域上形成电介质层中的接触和沟道的方法。联系人自行对齐。接触和通道由（1）在电介质层中形成接触开口形成，（2）在电介质层中形成通道开口，其中通道开口包围接触开口，（3）延伸接触开口以露出所述半导体衬底上的所述区域的部分; 和（4）分别用导电材料填充接触开口和通道开口以形成接触和通道。

7. 发明授权

US06596623B1 Use of organic spin on materials as a stop-layer for local interconnect, contact and via layers 有权
标题翻译：在材料上使用有机旋涂作为局部互连，接触和通孔层的终止层
公开(公告)号：US06596623B1
公开(公告)日：2003-07-22
申请号：US09527871
申请日：2000-03-17
申请人： Ramkumar Subramanian , Wenge Yang
发明人： Ramkumar Subramanian , Wenge Yang
IPC分类号： H01L214763
CPC分类号： H01L21/76895 , H01L21/02118 , H01L21/0212 , H01L21/3127 , H01L21/76802 , H01L21/76834
摘要： The present invention relates to a methodology of fabricating a local interconnect. The methodology includes the steps of forming an organic stop layer over a semiconductor structure having at least one conductive region, forming an insulating layer over the organic layer, forming a photoresist layer over the insulating layer, patterning the photoresist layer with at least one opening above the at least one conductive region, etching at least one opening in the insulating layer, concurrently stripping the photoresist layer and an exposed portion of the organic layer and filling the at least one opening with a conductive material to form the local interconnect.
摘要翻译：本发明涉及制造局部互连的方法。该方法包括以下步骤：在具有至少一个导电区域的半导体结构上形成有机阻挡层，在有机层上形成绝缘层，在绝缘层上形成光致抗蚀剂层，在至少一个开口上方形成光致抗蚀剂层所述至少一个导电区域，蚀刻所述绝缘层中的至少一个开口，同时剥离所述光致抗蚀剂层和所述有机层的暴露部分，并用导电材料填充所述至少一个开口以形成所述局部互连。

8. 发明授权

US06365509B1 Semiconductor manufacturing method using a dielectric photomask 有权
标题翻译：半导体制造方法采用棒式光掩模
公开(公告)号：US06365509B1
公开(公告)日：2002-04-02
申请号：US09586556
申请日：2000-05-31
申请人： Ramkumar Subramanian , Wenge Yang , Marina V. Plat , Lewis Shen
发明人： Ramkumar Subramanian , Wenge Yang , Marina V. Plat , Lewis Shen
IPC分类号： H01L214763
CPC分类号： H01L21/76802 , H01L21/76895 , H01L27/115
摘要： A method is provided for manufacturing a semiconductor with fewer steps and minimized variation in the etching process by using SiON as a bottom antireflective (BARC) layer and hard mask in conjunction with a thin photoresist layer. In one embodiment, an etch-stop layer is deposited on a semiconductor substrate, a dielectric layer is deposited on top of the etch-stop layer, a BARC is deposited on top of the dielectric layer, and a photoresist layer with a thickness less than the thickness of the BARC is then deposited on top of the BARC. The photoresist is then patterned, photolithographically processed, and developed. The BARC is then etched away in the pattern developed on the photoresist and to photoresist is then removed. The BARC is then used as a mask for the etching of the dielectric layer and is subsequently removed in the process of etchings the dielectric and etch-stop layers without the benefit of a separate BARC-removal step.
摘要翻译：提供了一种通过使用SiON作为底部抗反射（BARC）层和与薄的光致抗蚀剂层结合的硬掩模来制造具有较少步骤和最小化蚀刻工艺的半导体的方法。在一个实施例中，蚀刻停止层沉积在半导体衬底上，电介质层沉积在蚀刻停止层的顶部，BARC沉积在电介质层的顶部，并且光致抗蚀剂层的厚度小于然后将BARC的厚度沉积在BARC的顶部。然后将光致抗蚀剂图案化，光刻加工和显影。然后将BARC以在光致抗蚀剂上显影的图案蚀刻掉，然后除去光致抗蚀剂。然后将BARC用作蚀刻电介质层的掩模，随后在蚀刻电介质层和蚀刻停止层的过程中除去，而不需要单独的BARC去除步骤。

9. 发明授权

US06423612B1 Method of fabricating a shallow trench isolation structure with reduced topography 失效
标题翻译：制造具有减小的地形的浅沟槽隔离结构的方法
公开(公告)号：US06423612B1
公开(公告)日：2002-07-23
申请号：US09604547
申请日：2000-06-26
申请人： Wenge Yang , John Jianshi Wang , Fei Wang
发明人： Wenge Yang , John Jianshi Wang , Fei Wang
IPC分类号： H01L21336
CPC分类号： H01L21/76224
摘要： A shallow trench isolation (STI) region is covered with a nitride layer. The nitride layer, advantageously, fills in gaps in the underlying dielectric layer, such as seams, thereby reducing leakage. The nitride layer may be patterned to form a spacer above the STI region which is used to define an opening in the polysilicon layer that is subsequently deposited. The polysilicon layer is etched back to expose the nitride spacer, which is then etched away in a controlled fashion. Thus, a small opening may be formed in the polysilicon layer. Further, because the polysilicon layer is etched back to the top of the nitride spacer, the polysilicon layer is planarized thereby reducing stringers in subsequent processing.
摘要翻译：浅沟槽隔离（STI）区域被氮化物层覆盖。有利地，氮化物层填充下面的介电层中的间隙，例如接缝，从而减少泄漏。可以对氮化物层进行图案化以在STI区域上形成间隔物，其用于限定随后沉积的多晶硅层中的开口。蚀刻多晶硅层以暴露氮化物间隔物，然后以受控的方式将其去掉。因此，可以在多晶硅层中形成小开口。此外，由于多晶硅层被回蚀刻到氮化物间隔物的顶部，所以多晶硅层被平坦化，从而在随后的处理中减少桁条。

10. 发明授权

US06452225B1 Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride 有权
标题翻译：使用抗蚀剂掩模和蚀刻的氮氧化硅蚀刻存储单元多晶硅栅极层的方法和结构
公开(公告)号：US06452225B1
公开(公告)日：2002-09-17
申请号：US09617820
申请日：2000-07-17
申请人： Wenge Yang , Lewis Shen
发明人： Wenge Yang , Lewis Shen
IPC分类号： H01L29788
CPC分类号： H01L27/11517 , Y10S438/942 , Y10S438/95
摘要： A resist mask pattern having a reduced thickness is formed overlying on a silicon oxynitride film during formation of a memory gate. The resist mask pattern has a resist thickness (3000 to 4000 Angstroms) sufficient to withstand removal during etching of the silicon oxynitride film. The silicon oxynitride film, having a thickness of about 800 to 1500 Angstroms, is etched based on the resist mask pattern and then used as a mask pattern to etch the polysilicon gate layer underlying the silicon oxynitride layer, to expose a portion of an isolation region aligned relative to the resist mask pattern. The portion of the resist mask remaining after etching, in combination with the etched silicon oxynitride film, have a sufficient overall thickness to serve as a channel implant mask. Use of the resist mask pattern having the reduced thickness improves yield by minimizing the occurrence of misregistration, and enables reliable formation of spaces in the mask pattern having widths of less than 0.25 microns using conventional deep ultraviolet (DUV) photolithography techniques.
摘要翻译：在形成存储器栅极期间，在氧氮化硅膜上形成厚度减小的抗蚀剂掩模图案。抗蚀剂掩模图案具有足以在蚀刻氮氧化硅膜期间耐受去除的抗蚀剂厚度（3000至4000埃）。基于抗蚀剂掩模图案蚀刻具有约800至1500埃厚度的氧氮化硅膜，然后用作掩模图案以蚀刻氮氧化硅层下面的多晶硅栅极层，以暴露部分隔离区域相对于抗蚀剂掩模图案对准。蚀刻后残留的抗蚀剂掩模的部分与蚀刻的氮氧化硅膜组合，具有足够的总厚度以用作沟道注入掩模。使用具有减小的厚度的抗蚀剂掩模图案通过最小化不对准的发生来提高产率，并且使用常规的深紫外（DUV）光刻技术，可以在宽度小于0.25微米的掩模图案中可靠地形成空间。

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